AX2000 datasheet(57/262 Pages) MICROSEMI

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Axcelerator Family FPGAs

Re vi s i on 18

2 - 43

Voltage-Referenced I/O Standards

GTL+

Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It requires a differential

amplifier input buffer and an Open Drain output buffer. The VCCI pin should be connected to 2.5 V or

3.3 V. Note that 2.5 V GTL+ is not supported across the full military temperature range.

AC Loadings

Timing Characteristics

Table 2-37 • DC Input and Output Levels

VIL

VIH

VOL

VOH

IOL

IOH

Min., V

Max., V

Min., V

Max., V

Min., V

N/A

VREF – 0.1

VREF + 0.1

N/A

0.6

Figure 2-19 • AC Test Loads

Table 2-38 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

VREF (typ) (V)

Cload (pF)

VREF – 0.2

VREF + 0.2

VREF

1.0

Note:

* Measuring Point = VTRIP

Test Point

10 pF

VTT

Table 2-39 • 2.5 V GTL+ I/O Module

Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 2.3 V, TJ = 70°C

–2 Speed

–1 Speed

Std Speed

Units

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

2.5 V GTL+ I/O Module Timing

tDP

Input Buffer

1.71

1.95

2.29

tPY

Output Buffer

1.13

1.29

1.52

tICLKQ

Clock-to-Q for the I/O input register

0.67

0.77

0.90

tOCLKQ

Clock-to-Q for the I/O output register and

the I/O enable register

0.67

0.77

0.90

tSUD

Data Input Set-Up

0.23

0.27

0.31

tSUE

Enable Input Set-Up

0.26

0.30

0.35

tHD

Data Input Hold

0.00

tHE

Enable Input Hold

0.00

tCPWHL

Clock Pulse Width High to Low

0.39

tCPWLH

Clock Pulse Width Low to High

0.39

tWASYN

Asynchronous Pulse Width

0.37

tREASYN

Asynchronous Recovery Time

0.13

0.15

0.17

tHASYN

Asynchronous Removal Time

0.00

tCLR

Asynchronous Clear-to-Q

0.23

0.27

0.31

tPRESET

Asynchronous Preset-to-Q

0.23

0.27

0.31

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