AX2000 datasheet(29/262 Pages) MICROSEMI

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Axcelerator Family FPGAs

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Table 2-13 summarizes the different combinations of voltages and I/O standards that can be used

together in the same I/O bank.

Note that two I/O standards are compatible if:

•

Their VCCI values are identical.

•

Their VREF standards are identical (if applicable).

For example, if LVTTL 3.3 V (VREF= 1.0 V) is used, then the other available (i.e. compatible) I/O

standards in the same bank are LVTTL 3.3 V PCI/PCI-X, GTL+, and LVPECL.

Also note that when multiple I/O standards are used within a bank, the voltage tolerance will be limited to

the minimum tolerance of all I/O standards used in the bank.

Table 2-13 • Legal I/O Usage Matrix

I/O Standard

LVTTL 3.3 V (VREF=1.0 V)

–––

––

–

LVTTL 3.3 V(VREF=1.5 V)

–––

––

–

LVCMOS 2.5 V (VREF=1.0 V)

–

––

–

––

–

LVCMOS 2.5 V (VREF=1.25V)

–

––

–

LVCMOS1.8 V

–

––

–

LVCMOS1.5 V (VREF = 1.75 V) (JESD8-11)

–

––

–

––

–

3.3 V PCI/PCI-X (VREF = 1.0 V)

–––

––

–

3.3 V PCI/PCI-X (VREF= 1.5 V)

–––

––

–

GTL + (3.3 V)

–––

––

–

GTL + (2.5 V)

–

––

–

––

–

HSTL Class I

–

––

–

––

–

SSTL2 Class I & II

–

––

–

SSTL3 Class I & II

–––

––

–

LVDS (VREF = 1.0 V)

–

––

–

––

–

LVDS (VREF = 1.25 V)

–

––

–

LVPECL (VREF = 1.0 V)

–––

––

–

LVPECL (VREF = 1.5 V)

–––

––

–

Notes:

1. Note that GTL+ 2.5 V is not supported across the full military temperature range.

2. A "

✓" indicates whether standards can be used within a bank at the same time.

Examples:

a) LVTTL can be used with 3.3V PCI and GTL+ (3.3V), when VREF = 1.0V (GTL+ requirement).

b) LVTTL can be used with 3.3V PCI and SSTL3 Class I and II, when VREF = 1.5V (SSTL3 requirement).

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