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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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AX2000 数据表(PDF) 92 Page - Microsemi Corporation |
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AX2000 数据表(HTML) 92 Page - Microsemi Corporation |
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92 / 262 page  Detailed Specifications 2- 78 R e v i sio n 1 8 PLL Configurations The following rules apply to the different PLL inputs and outputs: Reference Clock The RefCLK can be driven by (Figure 2-50): 1. Global routed clocks (CLKE/F/G/H) or user-created clock network 2. CLK1 output of an adjacent PLL 3. [H]CLKxP (single-ended or voltage-referenced) 4. [H]CLKxP/[H]CLKxN pair (differential modes like LVPECL or LVDS) Feedback Clock The feedback clock can be driven by (Figure 2-51 on page 2-78): 1. Global routed clocks (CLKE/F/G/H) or user-created clock network 2. External [H]CLKxP/N I/O pad(s) from the adjacent PLL cell 3. An internal signal from the PLL block Figure 2-50 • Reference Clock Connections Figure 2-51 • Feedback Clock Connections Non-clock Pins P N INBUF PLL RefCLK RefCLK PLL RefCLK PLL PLL CLK1 Regular, LVPECL, or LVDS IOPAD Any macro from the core, except HCLK nets For cascading Logic PLL FB FB PLL PLLOUT/PLLRCLK Any macro except HCLK macros |
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