AX2000 datasheet(25/262 Pages) MICROSEMI

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Axcelerator Family FPGAs

Re vi s i on 18

2 - 11

User I/Os2

Introduction

The Axcelerator family features a flexible I/O structure, supporting a range of mixed voltages (1.5 V,

1.8 V, 2.5 V, and 3.3 V) with its bank-selectable I/Os. Table 2-8 on page 2-12 contains the I/O standards

supported by the Axcelerator family, and Table 2-10 on page 2-12 compares the features of the different

I/O standards.

Each I/O provides programmable slew rates, drive strengths, and weak pull-up and weak pull-down

circuits. The slew rate setting is effective for both rising and falling edges.

I/O standards, except 3.3 V PCI and 3.3 V PCI-X, are capable of hot insertion. 3.3 V PCI and 3.3 V PCI-

X are 5 V tolerant with the aid of an external resistor.

The input buffer has an optional user-configurable delay element. The element can reduce or eliminate

the hold time requirement for input signals registered within the I/O cell. The value for the delay is set on

a bank-wide basis. Note that the delay WILL be a function of process variations as well as temperature

and voltage changes.

Each I/O includes three registers: an input (InReg), an output (OutReg), and an enable register (EnReg).

I/Os are organized into banks, and there are eight banks per device—two per side (Figure 2-6 on

page 2-18). Each I/O bank has a common VCCI, the supply voltage for its I/Os.

For voltage-referenced I/Os, each bank also has a common reference-voltage bus, VREF. While VREF

must have a common voltage for an entire I/O bank, its location is user-selectable. In other words, any

user I/O in the bank can be selected to be a VREF.

The location of the VREF pin should be selected according to the following rules:

•

Any pin that is assigned as a VREF can control a maximum of eight user I/O pad locations in each

direction (16 total maximum) within the same I/O bank.

•

I/O pad locations listed as no connects are counted as part of the 16 maximum. In many cases,

this leads to fewer than eight user I/O package pins in each direction being controlled by a VREF

pin.

•

Dedicated I/O pins such as GND and VCCI are counted as part of the 16.

•

The two user I/O pads immediately adjacent on each side of the VREF pin (four in total) may only

be used as inputs. The exception is when there is a VCCI/GND pair separating the VREF pin and

the user I/O pad location.

•

The user does not need to assign VREF pins for OUTBUF and TRIBUF. VREF pins are needed

only for input and bidirectional I/Os.

The differential amplifier supply voltage VCCDA should be connected to 3.3 V.

A user can gain access to the various I/O standards in three ways:

•

Instantiate specific library macros that represent the desired specific standard.

•

Use generic I/O macros and then use Designer’s PinEditor to specify the desired I/O standards

(please note that this is not applicable to differential standards).

•

A combination of the first two methods.

Refer to the I/O Features in Axcelerator Family Devices application note and the Antifuse Macro Library

Guide

for more details.

Do not use an external resister to pull the I/O above VCCI for a higher logic “1” voltage level. The desired higher logic “1”

voltage level will be degraded due to a small I/O current, which exists when the I/O is pulled up above VCCI.

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