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数据搜索系统，热门电子元器件搜索 |
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AX2000 数据表(PDF) 93 Page - Microsemi Corporation |
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AX2000 数据表(HTML) 93 Page - Microsemi Corporation |
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93 / 262 page  Axcelerator Family FPGAs Re vi s i on 18 2 - 79 CLK1 and CLK2 Both PLL outputs, CLK1 and CLK2, can be used to drive a global resource, an adjacent PLL RefCLK input, or a net in the FPGA core. Not all drive combinations are possible (Table 2-81). Restrictions on CLK1 and CLK2 • When both are driving global resources, they must be driving the same type of global resource (i.e. either HCLK or CLK). • Only one can drive a routed net at any given time. Table 2-82 and Table 2-83 specify all the possible CLK1 and CLK2 connections for the north and south PLLs. HCLK1 and HCLK2 are used to denote the different HCLK networks when two are being driven at the same time by a single PLL (Note that HCLK1 is the primary clock resource associated with the PLL, and HCLK2 is the clock resource associated with the adjacent PLL). Likewise, CLK1 and CLK2 are used to denote the different CLK networks when two are being driven at the same time by a single PLL (Figure 2-48 on page 2-75). Table 2-81 • PLL General Connections Rules CLK1 CLK2 HCLK HCLK CLK CLK HCLK Routed net output Routed net output HCLK HCLK NONE NONE HCLK CLK NONE NONE CLK Note: The PLL outputs remain Low when REFCLK is constant (either Low or High). Table 2-82 • North PLL Connections CLK1 CLK2 HCLK1 Routed net HCLK1 Unused HCLK2 HCLK1 HCLK2 Routed net HCLK2 Both HCLK1 and routed net HCLK2 Unused Unused HCLK1 Unused Routed net Unused Both HCLK1 and routed net Unused Unused Routed net HCLK1 Routed net Unused Both HCLK1 and HCLK2 Routed net Both HCLK1 and HCLK2 Unused Both HCLK1 and routed net Unusable Both HCLK2 and routed net HCLK1 Both HCLK2 and routed net Unused HCLK1, HCLK2, and routed net Unusable Note: Designer software currently does not support all of these connections. Only exclusive connections where one output connects to a single net are supported at this time (e.g.CLK1 driving HCLK1, and HCLK2 is not supported). |
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