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AX2000 数据表(PDF) 86 Page - Microsemi Corporation |
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AX2000 数据表(HTML) 86 Page - Microsemi Corporation |
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86 / 262 page ![]() Detailed Specifications 2- 72 R e v i sio n 1 8 The HM and CM modules can select between: • The HCLK or CLK source respectively • A local signal routed on generic routing resources This allows each core tile to have eight clocks independent of the other core tiles in the device. Both HCLK and CLK are segmentable, meaning that individual branches of the global resource can be used independently. Like the HM and CM modules, the HD and RD modules can select between: • The HCLK or CLK source from the HM or CM module respectively • A local signal routed on generic routing resources The AX architecture is capable of supporting a large number of local clocks—24 segments per HCLK driving north-south and 28 segments per CLK driving east-west per core tile. Microsemi's Designer software’s place-and-route takes advantage of the segmented clock structure found in Axcelerator devices by turning off any unused clock segments. This results in not only better performance but also lower power consumption. Global Resource Access Macros Global resources can be driven by one of three sources: external pad(s), an internal net, or the output of a PLL. These connections can be made by using one of three types of macros: CLKBUF, CLKINT, and PLLCLK. CLKBUF and HCLKBUF CLKBUF (HCLKBUF) is used to drive a CLK (HCLK) from external pads. These macros can be used either generically or with the specific I/O standard desired (e.g. CLKBUF_LVCMOS25, HCLKBUF_LVDS, etc.) (Figure 2-42). Package pins CLKEP and CLKEN are associated with CLKE; package pins HCLKAP and HCLKAN are associated with HCLKA, etc. Note that when CLKBUF (HCLKBUF) is used with a single-ended I/O standard, it must be tied to the P-pad of the CLK (HCLK) package pin. In this case, the CLK (HCLK) N-pad can be used for user signals. CLKINT and HCLKINT CLKINT (HCLKINT) is used to access the CLK (HCLK) resource internally from the user signals (Figure 2-43). Figure 2-42 • CLKBUF and HCLKBUF Figure 2-43 • CLKINT and HCLKINT P N CLKBUF HCLKBUF Clock Network CLKINT HCLKINT Clock Network Logic |
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