AX2000 datasheet(27/262 Pages) MICROSEMI

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Axcelerator Family FPGAs

Re vi s i on 18

2 - 13

5V Tolerance

There are two schemes to achieve 5 V tolerance:

1. 3.3 V PCI and 3.3 V PCI-X are the only I/O standards that directly allow 5 V tolerance. To

implement this, an internal clamp diode between the input pad and the VCCI pad is enabled so

that the voltage at the input pin is clamped, as shown in EQ 3:

Vinput = VCCI + Vdiode = 3.3 V + 0.7 V = 4.0 V

EQ 3

The internal VCCI clamp diode is only enabled while the device is powered on, so the voltage at the input

will not be clamped if the VCCI or VCCA are powered off. An external series resistor (~100 Ω) is required

between the input pin and the 5 V signal source to limit the current to less than 20 mA (Figure 2-3). The

100 Ω resistor was chosen to meet the input Tr/Tf requirement (Table 2-19 on page 2-21). The GND

clamp diode is available for all I/O standards and always enabled.

2. 5 V tolerance can also be achieved with 3.3 V I/O standards (3.3 V PCI, 3.3 V PCI-X, and LVTTL)

using a bus-switch product (e.g. IDTQS32X2384). This will convert the 5 V signal to a 3.3 V signal

with minimum delay (Figure 2-4).

Simultaneous Switching Outputs (SSO)

When multiple output drivers switch simultaneously, they induce a voltage drop in the chip/package

power distribution. This simultaneous switching momentarily raises the ground voltage within the device

relative to the system ground. This apparent shift in the ground potential to a non-zero value is known as

simultaneous switching noise (SSN) or more commonly, ground bounce.

SSN becomes more of an issue in high pin count packages and when using high performance devices

such as the Axcelerator family. Based upon testing, Microsemi recommends that users not exceed eight

simultaneous switching outputs (SSO) per each VCCI/GND pair. To ease this potential burden on

designers, Microsemi has designed all of the Axcelerator BGAs3 to not exceed this limit with the

exception of the CS180, which has an I/O to VCCI/GND pair ratio of nine to one.

Please refer to the Simultaneous Switching Noise and Signal Integrity application note for more

information.

Figure 2-3 •

Use of an External Resistor for 5 V Tolerance

Figure 2-4 •

Bus Switch IDTQS32X2384

The user should note that in Bank 8 of both AX1000-FG484 and AX500-FG484, there are local violations of this 8:1 ratio.

Non-Microsemi Part

Mirosemi FPGA

5 V

3.3 V

VCCI

clamp

diode

Rext

GND

Clamp

Diode

5 V

3.3 V

20X

5 V

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