AX2000 datasheet(24/262 Pages) MICROSEMI

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Detailed Specifications

2- 10

R e v i sio n 1 8

User-Defined Supply Pins

VREF

Supply Voltage

Reference voltage for I/O banks. VREF pins are configured by the user from regular I/O pins; VREF pins

are not in fixed locations. There can be one or more VREF pins in an I/O bank.

Global Pins

HCLKA/B/C/D

Dedicated (Hardwired) Clocks A, B, C and D

These pins are the clock inputs for sequential modules or north PLLs. Input levels are compatible with all

supported I/O standards. There is a P/N pin pair for support of differential I/O standards. Single-ended

clock I/Os can only be assigned to the P side of a paired I/O. This input is directly wired to each R-cell

and offers clock speeds independent of the number of R-cells being driven. When the HCLK pins are

unused, it is recommended that they are tied to ground.

CLKE/F/G/H

Routed Clocks E, F, G, and H

These pins are clock inputs for clock distribution networks or south PLLs. Input levels are compatible with

all supported I/O standards. There is a P/N pin pair for support of differential I/O standards. Single-ended

clock I/Os can only be assigned to the P side of a paired I/O. The clock input is buffered prior to clocking

the R-cells. When the CLK pins are unused, Microsemi recommends that they are tied to ground.

JTAG/Probe Pins

PRA/B/C/D

Probe A, B, C and D

The Probe pins are used to output data from any user-defined design node within the device (controlled

with Silicon Explorer II). These independent diagnostic pins can be used to allow real-time diagnostic

output of any signal path within the device. The pins’ probe capabilities can be permanently disabled to

protect programmed design confidentiality. The probe pins are of LVTTL output levels.

TCK

Test Clock

Test clock input for JTAG boundary-scan testing and diagnostic probe (Silicon Explorer II).

TDI

Test Data Input

Serial input for JTAG boundary-scan testing and diagnostic probe. TDI is equipped with an internal 10 k

pull-up resistor.

TDO

Test Data Output

Serial output for JTAG boundary-scan testing.

TMS

Test Mode Select

The TMS pin controls the use of the IEEE 1149.1 boundary-scan pins (TCK, TDI, TDO, TRST). TMS is

equipped with an internal 10 k

Ω pull-up resistor.

TRST

Boundary Scan Reset Pin

The TRST pin functions as an active-low input to asynchronously initialize or reset the boundary scan

circuit. The TRST pin is equipped with a 10 k

Ω pull-up resistor.

Special Functions

Low Power Pin

The LP pin controls the low power mode of Axcelerator devices. The device is placed in the low power

mode by connecting the LP pin to logic high. To exit the low power mode, the LP pin must be set Low.

Additionally, the LP pin must be set Low during chip powering-up or chip powering-down operations. See

"Low Power Mode" on page 2-106 for more details.

No Connection

This pin is not connected to circuitry within the device. These pins can be driven to any voltage or can be

left floating with no effect on the operation of the device.

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