数据搜索系统，热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

预览 PDF HTML

AX2000 数据表(PDF) 43 Page - Microsemi Corporation

部件名 AX2000
功能描述  Axcelerator Family FPGAs
PDF  262 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  MICROSEMI [Microsemi Corporation]
网页  http://www.microsemi.com
标志 MICROSEMI - Microsemi Corporation

AX2000 数据表(HTML) 43 Page - Microsemi Corporation

Back Button AX2000 Datasheet HTML 39Page - Microsemi Corporation AX2000 Datasheet HTML 40Page - Microsemi Corporation AX2000 Datasheet HTML 41Page - Microsemi Corporation AX2000 Datasheet HTML 42Page - Microsemi Corporation AX2000 Datasheet HTML 43Page - Microsemi Corporation AX2000 Datasheet HTML 44Page - Microsemi Corporation AX2000 Datasheet HTML 45Page - Microsemi Corporation AX2000 Datasheet HTML 46Page - Microsemi Corporation AX2000 Datasheet HTML 47Page - Microsemi Corporation Next Button
Zoom Inzoom in Zoom Outzoom out
 43 / 262 page
background image
Axcelerator Family FPGAs
Re vi s i on 18
2 - 29
LVTTL Output Drive Strength = 4 (24 mA) / Low Slew Rate
tDP
Input Buffer
1.68
1.92
2.26
ns
tPY
Output Buffer
10.45
11.90
13.99
ns
tENZL
Enable to Pad Delay through the Output Buffer—Z to
Low
10.61
12.08
14.21
ns
tENZH
Enable to Pad Delay through the Output Buffer—Z to
High
10.47
11.93
14.02
ns
tENLZ
Enable to Pad Delay through the Output Buffer—Low
to Z
1.92
1.94
1.94
ns
tENHZ
Enable to Pad Delay through the Output Buffer—High
to Z
2.57
2.58
2.59
ns
tIOCLKQ
Sequential Clock-to-Q for the I/O Input Register
0.67
0.77
0.90
ns
tIOCLKY
Clock-to-output Y for the I/O Output Register and the
I/O Enable Register
0.67
0.77
0.90
ns
tSUD
Data Input Set-Up
0.23
0.27
0.31
ns
tSUE
Enable Input Set-Up
0.26
0.30
0.35
ns
tHD
Data Input Hold
0.00
0.00
0.00
ns
tHE
Enable Input Hold
0.00
0.00
0.00
ns
tCPWHL
Clock Pulse Width High to Low
0.39
0.39
0.39
ns
tCPWLH
Clock Pulse Width Low to High
0.39
0.39
0.39
ns
tWASYN
Asynchronous Pulse Width
0.37
0.37
0.37
ns
tREASYN
Asynchronous Recovery Time
0.13
0.15
0.17
ns
tHASYN
Asynchronous Removal Time
0.00
0.00
0.00
ns
tCLR
Asynchronous Clear-to-Q
0.23
0.27
0.31
ns
tPRESET
Asynchronous Preset-to-Q
0.23
0.27
0.31
ns
Table 2-22 • 3.3 V LVTTL I/O Module
Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 70°C (continued)
–2 Speed
–1 Speed
Std Speed
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max. Units



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com