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AX2000 数据表(PDF) 37 Page - Microsemi Corporation |
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AX2000 数据表(HTML) 37 Page - Microsemi Corporation |
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37 / 262 page ![]() Axcelerator Family FPGAs Re vi s i on 18 2 - 23 I/O Module Timing Characteristics Figure 2-11 • Timing Model Figure 2-12 • Input Register Timing Characteristics OutReg PRE/CLR EnReg PRE/CLR InReg PRE/CLR CLK (Routed or Hardwired) Output Register Output Enable Register Input Register E E E DQ D Q DQ E D Q CLR PRESET CLK tSUE tHE tSUD tHD tICLKQ tWASYN tHASYN tCLR tREASYN tCPWHL tCPWLH tPRESET tWASYN tHASYN tREASYN |
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