AX2000 datasheet(99/262 Pages) MICROSEMI

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Axcelerator Family FPGAs

Re vi s i on 18

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Clock Skew Minimization

Figure 2-56 indicates how feedback from the clock network can be used to create minimal skew between

the distributed clock network and the input clock. The input clock is fed to the reference clock input of the

PLL. The output clock (CLK2) feeds a routed clock network. The feedback input to the PLL uses a clock

input delayed by a routing network. The PLL then adjusts the phase of the input clock to match the

delayed clock, thus providing nearly zero effective skew between the two clocks. Refer to the Axcelerator

Family PLL and Clock Management

application note for more information.

Figure 2-56 • Using the PLL for Clock Deskewing

QCLR

Delay Line

PLL

RefCLK

CLK1

Power-Down

Input Clock

Clock Network

Lock

CLK2

FBMuxSel

DividerI

DelayLine

DividerJ

LowFreq

Osc

133 MHz

SET

133 MHz

Delay Line

/i Delay

Match

/i Delay

Match

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