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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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AX2000 数据表(PDF) 102 Page - Microsemi Corporation |
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AX2000 数据表(HTML) 102 Page - Microsemi Corporation |
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102 / 262 page  Detailed Specifications 2- 88 R e v i sio n 1 8 Note that the RAM blocks employ little-endian byte order for read and write operations. Modes of Operation There are two read modes and one write mode: • Read Nonpipelined (synchronous – one clock edge) • Read Pipelined (synchronous – two clock edges) • Write (synchronous – one clock edge) In the standard read mode, new data is driven onto the RD bus in the clock cycle immediately following RA and REN valid. The read address is registered on the read-port active-clock edge and data appears at read-data after the RAM access time. Setting the PIPE to OFF enables this mode. The pipelined mode incurs an additional clock delay from address to data, but enables operation at a much higher frequency. The read-address is registered on the read-port active-clock edge, and the read data is registered and appears at RD after the second read clock edge. Setting the PIPE to ON enables this mode. On the write active-clock edge, the write data are written into the SRAM at the write address when WEN is high. The setup time of the write address, write enables, and write data are minimal with respect to the write clock. Write and read transfers are described with timing requirements beginning in the "Timing Characteristics" section on page 2-89. Table 2-88 • RAM Signal Description Signal Direction Description WCLK Input Write clock (can be active on either edge). WA[J:0] Input Write address bus.The value J is dependent on the RAM configuration and the number of cascaded memory blocks. The valid range for J is from 6 to15. WD[M-1:0] Input Write data bus. The value M is dependent on the RAM configuration and can be 1, 2, 4, 9, 18, or 36. RCLK Input Read clock (can be active on either edge). RA[K:0] Input Read address bus. The value K is dependent on the RAM configuration and the number of cascaded memory blocks. The valid range for K is from 6 to 15. RD[N-1:0] Output Read data bus. The value N is dependent on the RAM configuration and can be 1, 2, 4, 9, 18, or 36. REN Input Read enable. When this signal is valid on the active edge of the clock, data at location RA will be driven onto RD. WEN Input Write enable. When this signal is valid on the active edge of the clock, WD data will be written at location WA. RW[2:0] Input Width of the read operation dataword. WW[2:0] Input Width of the write operation dataword. Pipe Input Sets the pipe option to be on or off. |
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