AX2000 datasheet(101/262 Pages) MICROSEMI

101 / 262 page

Axcelerator Family FPGAs

Re vi s i on 18

2 - 87

RAM

Each memory block consists of 4,608 bits that can be organized as 128x36, 256x18, 512x9, 1kx4, 2kx2,

or 4kx1 and are cascadable to create larger memory sizes. This allows built-in bus width conversion

(Table 2-86). Each block has independent read and write ports which enable simultaneous read and write

operations.

Clocks

The RCLK and the WCLK have independent source polarity selection and can be sourced by any global

or local signal.

RAM Configurations

The AX architecture allows the read side and write side of RAMs to be organized independently, allowing

for bus conversion. For example, the write side can be set to 256x18 and the read side to 512x9.

Both the write width and read width for the RAM blocks can be specified independently and changed

dynamically with the WW (write width) and RW (read width) pins. The D x W different configurations are:

128 x 36, 256 x 18, 512 x 9, 1k x 4, 2k x 2, and 4k x 1. The allowable RW and WW values are shown in

Table 2-87.

When widths of one, two, and four are selected, the ninth bit is unused. For example, when writing nine-

bit values and reading four-bit values, only the first four bits and the second four bits of each nine-bit

value are addressable for read operations. The ninth bit is not accessible. Conversely, when writing four-

bit values and reading nine-bit values, the ninth bit of a read operation will be undefined.

Table 2-86 • Memory Block WxD Options

Data-word (in bits)

Depth

Address Bus

Data Bus

4,096

RA/WA[11:0]

RD/WD[0]

2,048

RA/WA[10:0]

RD/WD[1:0]

1,024

RA/WA[9:0]

RD/WD[3:0]

512

RA/WA[8:0]

RD/WD[8:0]

256

RA/WA[7:0]

RD/WD[17:0]

128

RA/WA[6:0]

RD/WD[35:0]

Table 2-87 • Allowable RW and WW Values

RW(2:0)

WW(2:0)

D x W

000

4k x 1

001

2k x 2

010

1k x 4

011

512 x 9

100

256 x 18

101

128 x 36

11x

reserved

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