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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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AX2000 数据表(PDF) 105 Page - Microsemi Corporation |
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AX2000 数据表(HTML) 105 Page - Microsemi Corporation |
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105 / 262 page  Axcelerator Family FPGAs Re vi s i on 18 2 - 91 Table 2-90 • Two RAM Blocks Cascaded Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 70°C –2 Speed –1 Speed Std Speed Parameter Description Min. Max. Min. Max. Min. Max. Units Write Mode tWDASU Write Data Setup vs. WCLK 1.39 1.59 1.87 ns tWDAHD Write Data Hold vs. WCLK 0.00 0.00 0.00 ns tWADSU Write Address Setup vs. WCLK 1.39 1.59 1.87 ns tWADHD Write Address Hold vs. WCLK 0.00 0.00 0.00 ns tWENSU Write Enable Setup vs. WCLK 1.39 1.59 1.87 ns tWENHD Write Enable Hold vs. WCLK 0.00 0.00 0.00 ns tWCKH WCLK Minimum High Pulse Width 0.75 0.75 0.75 ns tWCLK WCLK Minimum Low Pulse Width 1.76 1.76 1.76 ns tWCKP WCLK Minimum Period 2.51 2.51 2.51 ns Read Mode tRADSU Read Address Setup vs. RCLK 1.71 1.94 2.28 ns tRADHD Read Address Hold vs. RCLK 0.00 0.00 0.00 ns tRENSU Read Enable Setup vs. RCLK 1.71 1.94 2.28 ns tRENHD Read Enable Hold vs. RCLK 0.00 0.00 0.00 ns tRCK2RD1 RCLK-To-OUT (Pipelined) 1.43 1.63 1.92 ns tRCK2RD2 RCLK-To-OUT (Non-Pipelined) 2.26 2.58 3.03 ns tRCLKH RCLK Minimum High Pulse Width 0.73 0.73 0.73 ns tRCLKL RCLK Minimum Low Pulse Width 1.89 1.89 1.89 ns tRCKP RCLK Minimum Period 2.62 2.62 2.62 ns Note: Timing data for these two cascaded RAM blocks uses a depth of 8,192. For all other combinations, use Microsemi’s timing software. |
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