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AX2000 数据表(PDF) 108 Page - Microsemi Corporation

部件名 AX2000
功能描述  Axcelerator Family FPGAs
PDF  262 Pages
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制造商  MICROSEMI [Microsemi Corporation]
网页  http://www.microsemi.com
标志 MICROSEMI - Microsemi Corporation

AX2000 数据表(HTML) 108 Page - Microsemi Corporation

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Detailed Specifications
2- 94
R e v i sio n 1 8
Table 2-93 • Sixteen RAM Blocks Cascaded
Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 70°C
–2 Speed
–1 Speed
Std Speed
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Units
Write Mode
tWDASU
Write Data Setup vs. WCLK
16.54
18.84
22.15
ns
tWDAHD
Write Data Hold vs. WCLK
0.00
0.00
0.00
ns
tWADSU
Write Address Setup vs. WCLK
16.54
18.84
22.15
ns
tWADHD
Write Address Hold vs. WCLK
0.00
0.00
0.00
ns
tWENSU
Write Enable Setup vs. WCLK
16.54
18.84
22.15
ns
tWENHD
Write Enable Hold vs. WCLK
0.00
0.00
0.00
ns
tWCKH
WCLK Minimum High Pulse Width
0.75
0.75
0.75
ns
tWCLK
WCLK Minimum Low Pulse Width
13.40
13.40
13.40
ns
tWCKP
WCLK Minimum Period
14.15
14.15
14.15
ns
Read Mode
tRADSU
Read Address Setup vs. RCLK
18.13
20.65
24.27
ns
tRADHD
Read Address Hold vs. RCLK
0.00
0.00
0.00
ns
tRENSU
Read Enable Setup vs. RCLK
18.13
20.65
24.27
ns
tRENHD
Read Enable Hold vs. RCLK
0.00
0.00
0.00
ns
tRCK2RD1
RCLK-To-OUT (Pipelined)
12.08
13.76
16.17
ns
tRCK2RD2
RCLK-To-OUT (Non-Pipelined)
12.83
14.62
17.18
ns
tRCLKH
RCLK Minimum High Pulse Width
0.73
0.73
0.73
ns
tRCLKL
RCLK Minimum Low Pulse Width
14.41
14.41
14.41
ns
tRCKP
RCLK Minimum Period
15.14
15.14
15.14
ns
Note:
Timing data for these sixteen cascaded RAM blocks uses a depth of 65,536. For all other combinations, use
Microsemi’s timing software.



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