AX2000 datasheet(110/262 Pages) MICROSEMI

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Detailed Specifications

2- 96

R e v i sio n 1 8

FIFO Flag Logic

The FIFO is user configurable into various DEPTHs and WIDTHs. Figure 2-62 shows the FIFO address

counter details.

•

Bits 11 to 5 are active for all modes.

•

As the data word size is reduced, more least-significant bits are added to the address.

•

As the number of cascaded blocks increases, the number of significant bits in the address

increases.

For example, if four blocks are cascaded as a 1kx16 FIFO with each block having a 1kx4 aspect ratio,

bits 11 to 2 of the address will be used to specify locations within each RAM block, whereas bits 13 and

12 will be used to specify the RAM block.

The AFULL and AEMPTY flag threshold values are programmable. The threshold values are AFVAL and

AEVAL, respectively. Although the trigger threshold for each flag is defined with eight bits, the effective

number of threshold bits in the comparison depends on the configuration. The effective number of

threshold bits corresponds to the range of active bits in the FIFO address space (Table 2-94).

Note:

Inactive counter bits are set to zero.

Figure 2-62 • FIFO Address Counters

Table 2-94 • FIFO Flag Logic

Mode

Inactive

AEVAL/AFVAL Bits

Inactive DIFF

Bits (set to 0)

DIFF Comparison to AFVAL/AEVAL

Non-cascade

[7:4]

[15:12]

DIFF[11:8] withAE/FVAL[3:0]

Cascade 2 blocks

[7:5]

[15:13]

DIFF[12:8] withAE/FVAL[4:0]

Cascade 4 blocks

[7:6]

[15:14]

DIFF[13:8] withAE/FVAL[5:0]

Cascade 8 blocks

[7]

[15]

DIFF[14:8] withAE/FVAL[6:0]

Cascade 16 blocks

None

DIFF[15:8] withAE/FVAL[7:0]

CNTR [12]

activate

FIFO Address Counters

>> REN [4:0], RAD [11:0]

>> WEN [4:0], WAD [11:0]

[12:W] [13:W]

[14:W]

[15:W]

128x36

1kx4

512x9

256x18

[11:5]

[11:4]

[11:3]

[11:2]

[11:1]

[11:0]

4kx1

2kx2

Variable Active Address Space

CNTR [15]

activate

CNTR [2]

activate

CNTR [3]

activate

CNTR [4]

activate

CNTR [11:5]

always active

CNTR [13]

activate

CNTR [14]

activate

CNTR [0]

activate

CNTR [1]

activate

Cas 16 blks

by 1

by 2

by 4

by 9

by 18

by 36

Cas 2 blks

Cas 4 blks

Cas 8 blks

Mode when

Active

Counter

Bits

R/W EN[3]

R/W ADD[0]

R/W ADD[1]

R/W ADD[2]

R/W ADD[3]

R/W ADD[7:5]

R/W ADD[11:8]

R/W EN[0]

R/W EN[1]

R/W EN[2]

R/W ADD[4]

FIFO Address

AEVAL/AFVAL[7]

not compared

AEVAL/AFVAL[3:0]

AEVAL/AFVAL[4]

AEVAL/AFVAL[5]

AEVAL/AFVAL[6]

CNTR [15:0]

Alignment of

Threshold bits

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