AX2000 datasheet(109/262 Pages) MICROSEMI

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Axcelerator Family FPGAs

Re vi s i on 18

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FIFO

Every memory block has its own embedded FIFO controller. Each FIFO block has one read port and one

write port. This embedded FIFO controller uses no internal FPGA logic and features:

•

Glitch-free FIFO Flags

•

Gray-code address counters/pointers to prevent metastability problems

•

Overflow and underflow control

Both ports are configurable in various sizes from 4k x 1 to 128 x 36, similar to the RAM block size. Each

port is fully synchronous.

Read and write operations can be completely independent. Data on the appropriate WD pins are written

to the FIFO on every active WCLK edge as long as WEN is high. Data is read from the FIFO and output

on the appropriate RD pins on every active RCLK edge as long as REN is asserted.

The FIFO block offers programmable almost-empty (AEMPTY) and almost-full (AFULL) flags as well as

EMPTY and FULL flags (Figure 2-61):

•

The FULL flag is synchronous to WCLK. It allows the FIFO to inhibit writing when full.

•

The EMPTY flag is synchronous to RCLK. It allows the FIFO to inhibit reading at the empty

condition.

Gray code counters are used to prevent metastability problems associated with flag logic. The depth of

the FIFO is dependent on the data width and the number of memory blocks used to create the FIFO. The

write operations to the FIFO are synchronous with respect to the WCLK, and the read operations are

synchronous with respect to the RCLK.

The FIFO block may be reset to the empty state.

Figure 2-61 • Axcelerator RAM with Embedded FIFO Controller

CNT 16

AFVAL

AEVAL

RCLK

WCLK

CLR

FWEN

FREN

DEPTH[3:0]

RD [n-1:0]

WD [n-1:0]

RCLK

WCLK

RA [J:0]

WA [J:0]

REN

WEN

FULL

AEMPTY

AFULL

EMPTY

RAM

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