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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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AX2000 数据表(PDF) 65 Page - Microsemi Corporation |
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AX2000 数据表(HTML) 65 Page - Microsemi Corporation |
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65 / 262 page  Axcelerator Family FPGAs Re vi s i on 18 2 - 51 Timing Characteristics Table 2-57 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) 1.2 – 0.125 1.2 + 0.125 1.2 Note: * Measuring Point = VTRIP Table 2-58 • LVDS I/O Module Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 2.3 V, TJ = 70°C –2 Speed –1 Speed Std Speed Units Parameter Description Min. Max. Min. Max. Min. Max. LVDS Output Module Timing tDP Input Buffer 1.80 2.05 2.41 ns tPY Output Buffer 2.32 2.64 3.11 ns tICLKQ Clock-to-Q for the I/O input register 0.67 0.77 0.90 ns tOCLKQ Clock-to-Q for the I/O output register and the I/O enable register 0.67 0.77 0.90 ns tSUD Data Input Set-Up 0.23 0.27 0.31 ns tSUE Enable Input Set-Up 0.26 0.30 0.35 ns tHD Data Input Hold 0.00 0.00 0.00 ns tHE Enable Input Hold 0.00 0.00 0.00 ns tCPWHL Clock Pulse Width High to Low 0.39 0.39 0.39 ns tCPWLH Clock Pulse Width Low to High 0.39 0.39 0.39 ns tWASYN Asynchronous Pulse Width 0.37 0.37 0.37 ns tREASYN Asynchronous Recovery Time 0.13 0.15 0.17 ns tHASYN Asynchronous Removal Time 0.00 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.23 0.27 0.31 ns tPRESET Asynchronous Preset-to-Q 0.23 0.27 0.31 ns |
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