AX2000 datasheet(68/262 Pages) MICROSEMI

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Detailed Specifications

2- 54

R e v i sio n 1 8

Module Specifications

C-Cell

Introduction

The C-cell is one of the two logic module types in the AX architecture. It is the combinatorial logic

resource in the Axcelerator device. The AX architecture implements a new combinatorial cell that is an

extension of the C-cell implemented in the SX-A family. The main enhancement of the new C-cell is the

addition of carry-chain logic.

The C-cell can be used in a carry-chain mode to construct arithmetic functions. If carry-chain logic is not

required, it can be disabled.

The C-cell features the following (Figure 2-27):

•

Eight-input MUX (data: D0-D3, select: A0, A1, B0, B1). User signals can be routed to any one of

these inputs. Any of the C-cell inputs (D0-D3, A0, A1, B0, B1) can be tied to one of the four routed

clocks (CLKE/F/G/H).

•

Inverter (DB input) can be used to drive a complement signal of any of the inputs to the C-cell.

•

A carry input and a carry output. The carry input signal of the C-cell is the carry output from the C-

cell directly to the north.

•

Carry connect for carry-chain logic with a signal propagation time of less than 0.1 ns.

•

A hardwired connection (direct connect) to the adjacent R-cell (Register Cell) for all C-cells on the

east side of a SuperCluster with a signal propagation time of less than 0.1 ns.

This layout of the C-cell (and the C-cell Cluster) enables the implementation of over 4,000 functions of up

to five bits. For example, two C-cells can be used together to implement a four-input XOR function in a

single cell delay.

The carry-chain configuration is handled automatically for the user with Microsemi's extensive macro

library (please see the Antifuse Macro Library Guide for a complete listing of available Axcelerator

macros).

Figure 2-27 • C-Cell

D1 D3

D0 D2

CFN FCI

FCO Y

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