AX2000 datasheet(90/262 Pages) MICROSEMI

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Detailed Specifications

2- 76

R e v i sio n 1 8

single-ended, or voltage-referenced standard. The [H]CLKxN pad can only be used as a differential pair

with [H]CLKxP.

The block marked “/i Delay Match” is a fixed delay equal to that of the i divider. The “/j Delay Match” block

has the same function as its j divider counterpart.

Functional Description

Figure 2-48 on page 2-75 illustrates a block diagram of the PLL. The PLL contains two dividers, i and j,

that allow frequency scaling of the clock signal:

•

The i divider in the feedback path allows multiplication of the input clock by integer factors ranging

from 1 to 64, and the resultant frequency is available at the output of the PLL block.

•

The j divider divides the PLL output by integer factors ranging from 1 to 64, and the divided clock

is available at CLK1.

•

The two dividers together can implement any combination of multiplication and division up to a

maximum frequency of 1 GHz on CLK1. Both the CLK1 and CLK2 outputs have a fixed 50/50

duty cycle.

•

The output frequencies of the two clocks are given by the following formulas (fREF is the reference

clock frequency):

fCLK1 = fREF * (DividerI) / (DividerJ)

EQ 4

fCLK2 = fREF * (DividerI)

EQ 5

•

CLK2 provides the PLL output directly—without division

The input and output frequency ranges are selected by LowFreq and Osc(2:0), respectively. These

functions and their possible values are detailed in Table 2-80 on page 2-77.

The delay lines shown in Figure 2-48 on page 2-75 are programmable. The feedback clock path can be

delayed (using the five DelayLine bits) relative to the reference clock (or vice versa) by up to 3.75 ns in

increments of 250 ps. Table 2-80 on page 2-77 describes the usage of these bits. The delay increments

are independent of frequency, so this results in phase changes that vary with frequency. The delay value

is highly dependent on VCC and the speed grade.

Figure 2-49 is a logical diagram of the various control signals to the PLL and shows how the PLL

interfaces with the global and routing networks of the FPGA. Note that not all signals are user-

accessible. These non-user-accessible signals are used by the place-and-route tool to control the

configuration of the PLL. The user gains access to these control signals either based upon the

connections built in the user's design or through the special macros (Table 2-84 on page 2-81) inserted

into the design. For example, connecting the macro PLLOUT to CLK2 will control the OUTSEL signal.

Note:

Not all signals are available to the user.

Figure 2-49 • PLL Logical Interface

RefCLK

CLK1

CLK2

REFSEL

ROOTSEL

FBMuxSEL

[H]CLKINT

[H]CLKxP

[H]CLKxN

I/O

Core net

CLK net

FBINT

CLKINT

CLK1 (PLLn-1)

[H]CLK

To PLLn+1

PLLSEL

OUTSEL

CLK Out

(Routed net out pin)

PLL

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