AX2000 datasheet(70/262 Pages) MICROSEMI

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Detailed Specifications

2- 56

R e v i sio n 1 8

Carry-Chain Logic

The Axcelerator dedicated carry-chain logic offers a very compact solution for implementing arithmetic

functions without sacrificing performance.

To implement the carry-chain logic, two C-cells in a Cluster are connected together so the FCO (i.e. carry

out) for the two bits is generated in a carry look-ahead scheme to achieve minimum propagation delay

from the FCI (i.e. carry in) into the two-bit Cluster. The two-bit carry logic is shown in Figure 2-29.

The FCI of one C-cell pair is driven by the FCO of the C-cell pair immediately above it. Similarly, the FCO

of one C-cell pair, drives the FCI input of the C-cell pair immediately below it (Figure 1-4 on page 1-3 and

Figure 2-30 on page 2-57).

The carry-chain logic is selected via the CFN input. When carry logic is not required, this signal is

deasserted to save power. Again, this configuration is handled automatically for the user through

Microsemi's macro library.

The signal propagation delay between two C-cells in the carry-chain sequence is 0.1 ns.

Figure 2-29 • Axcelerator’s Two-Bit Carry Logic

DCOUT

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