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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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AX2000 数据表(PDF) 13 Page - Microsemi Corporation |
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AX2000 数据表(HTML) 13 Page - Microsemi Corporation |
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13 / 262 page  Axcelerator Family FPGAs Re vi s i on 18 1-7 Design Environment The Axcelerator family of FPGAs is fully supported by both Microsemi's Libero® Integrated Design Environment and Designer FPGA Development software. Libero IDE is an integrated design manager that seamlessly integrates design tools while guiding the user through the design flow, managing all design and log files, and passing necessary design data among tools. Additionally, Libero IDE allows users to integrate both schematic and HDL synthesis into a single flow and verify the entire design in a single environment (see the Libero IDE Flow diagram located on the Microsemi SoC Products Group website). Libero IDE includes Synplify® Actel Edition (AE) from Synplicity®, ViewDraw® AE from Mentor Graphics®, ModelSim® HDL Simulator from Mentor Graphics, WaveFormer Lite™ AE from SynaptiCAD®, and Designer software from Microsemi. Designer software is a place-and-route tool and provides a comprehensive suite of backend support tools for FPGA development. The Designer software includes the following: • Timer – a world-class integrated static timing analyzer and constraints editor which support timing-driven place-and-route • NetlistViewer – a design netlist schematic viewer • ChipPlanner – a graphical floorplanner viewer and editor • SmartPower – allows the designer to quickly estimate the power consumption of a design • PinEditor – a graphical application for editing pin assignments and I/O attributes • I/O Attribute Editor – displays all assigned and unassigned I/O macros and their attributes in a spreadsheet format With the Designer software, a user can lock the design pins before layout while minimally impacting the results of place-and-route. Additionally, Microsemi’s back-annotation flow is compatible with all the major simulators and the simulation results can be cross-probed with Silicon Explorer II, Microsemi’s integrated verification and logic analysis tool. Another tool included in the Designer software is the SmartGen core generator, which easily creates popular and commonly used logic functions for implementation into your schematic or HDL design. Designer software is compatible with the most popular FPGA design entry and verification tools from EDA vendors, such as Mentor Graphics, Synplicity, Synopsys, and Cadence Design Systems. The Designer software is available for both the Windows and UNIX operating systems. Programming Programming support is provided through Silicon Sculptor II, a single-site programmer driven via a PC- based GUI. In addition, BP Microsystems offers multi-site programmers that provide qualified support for Microsemi devices. Factory programming is available for high-volume production needs. In-System Diagnostic and Debug Capabilities The Axcelerator family of FPGAs includes internal probe circuitry, allowing the designer to dynamically observe and analyze any signal inside the FPGA without disturbing normal device operation (Figure 1-9). Figure 1-9 • Probe Setup Serial Connection Additional 14 Channels (Logic Analyzer) Axcelerator FPGAs Silicon Explorer II TDI TCK TMS 16 Pin Connection 22 Pin Connection PRA PRB TDO CH3/PRC CH4/PRD |
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