AX2000 datasheet(112/262 Pages) MICROSEMI

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Detailed Specifications

2- 98

R e v i sio n 1 8

Glitch Elimination

An analog filter is added to each FIFO controller to guarantee glitch-free FIFO-flag logic.

Overflow and Underflow Control

The counter MSB keeps track of the difference between the read address (RA) and the write address

(WA). The EMPTY flag is set when the read and write addresses are equal. To prevent underflow, the

write address is double-sampled by the read clock prior to comparison with the read address (part A in

Figure 2-64). To prevent overflow, the read address is double-sampled by the write clock prior to

comparison to the write address (part B in Figure 2-64).

FIFO Configurations

Unlike the RAM, the FIFO's write width and read width cannot be specified independently. For the FIFO,

the write and read widths must be the same. The WIDTH pins are used to specify one of six allowable

word widths, as shown in Table 2-96.

The DEPTH pins allow RAM cells to be cascaded to create larger FIFOs. The four pins allow depths of 2,

4, 8, and 16 to be specified. Table 2-86 on page 2-87 describes the FIFO depth options for various data

width and memory blocks.

Interface

Figure 2-65 on page 2-99 shows a logic block diagram of the Axcelerator FIFO module.

Cascading FIFO Blocks

FIFO blocks can be cascaded to create deeper FIFO functions. When building larger FIFO blocks, if the

word width can be fractured in a multi-bit FIFO, the fractured word configuration is recommended over a

cascaded configuration. For example, 256x36 can be configured as two blocks of 256x18. This should be

taken into account when building the FIFO blocks manually. However, when using SmartGen, the user

only needs to specify the depth and width of the necessary FIFO blocks. SmartGen automatically

configures these blocks to optimize performance.

Figure 2-64 • Overflow and Underflow Control

Table 2-96 • FIFO Width Configurations

WIDTH(2:0)

W x D

000

1 x 4k

001

2 x 2k

010

4 x 1k

011

9 x 512

100

18 x 256

101

36 x 128

11x

reserved

EMPTY

RCLK

FULL

WCLK

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