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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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AX2000 数据表(PDF) 120 Page - Microsemi Corporation |
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AX2000 数据表(HTML) 120 Page - Microsemi Corporation |
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120 / 262 page  Detailed Specifications 2- 10 6 R ev isio n 1 8 Building RAM and FIFO Modules RAM and FIFO modules can be generated and included in a design in two different ways: • Using the SmartGen Core Generator where the user defines the depth and width of the FIFO/RAM, and then instantiates this block into the design (refer to the SmartGen, FlashROM, Analog System Builder, and Flash Memory System Builder User’s Guide for more information). • The alternative is to instantiate the RAM/FIFO blocks manually, using inverters for polarity control and tying all unused data bits to ground. Other Architectural Features Low Power Mode Although designed for high performance, the AX architecture also allows the user to place the device into a low power mode. Each I/O bank in an Axcelerator device can be configured individually, when in low power mode, to tristate all outputs, disable inputs, or both. The low power mode is activated by asserting the LP pin, which is grounded in normal operation. While in the low power mode, the device is still fully functional and all internal logic states are preserved. This allows a user to disable all but a few signals and operate the part in a low-frequency, watchdog Table 2-102 • Sixteen FIFO Blocks Cascaded Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 70°C –2 Speed –1 Speed Std Speed Units Parameter Description Min. Max. Min. Max. Min. Max. FIFO Module Timing tWSU Write Setup 16.32 18.60 21.86 ns tWHD Write Hold 0.00 0.00 0.00 ns tWCKH WCLK High 0.75 0.75 0.75 ns tWCKL WCLK Low 13.40 13.40 13.40 ns tWCKP Minimum WCLK Period 14.15 14.15 14.15 ns tRSU Read Setup 17.16 19.54 22.97 ns tRHD Read Hold 0.00 0.00 0.00 ns tRCKH RCLK High 0.73 0.73 0.73 ns tRCKL RCLK Low 14.41 14.41 14.41 ns tRCKP Minimum RCLK period 15.14 15.14 15.14 ns tCLRHF Clear High 0.00 0.00 0.00 ns tCLR2FF Clear-to-flag (EMPTY/FULL) 1.92 2.18 2.57 ns tCLR2AF Clear-to-flag (AEMPTY/AFULL) 4.39 5.00 5.88 ns tCK2FF Clock-to-flag (EMPTY/FULL) 2.13 2.42 2.85 ns tCK2AF Clock-to-flag (AEMPTY/AFULL) 5.04 5.75 6.75 ns tRCK2RD1 RCLK-To-OUT (Pipelined) 12.08 13.76 16.17 ns tRCK2RD2 RCLK-To-OUT (Nonpipelined) 12.83 14.62 17.18 ns Note: Timing data for these sixteen cascaded FIFO blocks uses a depth of 65,536. For all other combinations, use Microsemi’s timing software. |
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