PM0056 datasheet(52/156 Pages) STMICROELECTRONICS

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The Cortex-M3 instruction set

PM0056

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3.3.2

Restrictions when using PC or SP

Many instructions have restrictions on whether you can use the program counter (PC) or

stack pointer (SP) for the operands or destination register. See instruction descriptions for

more information.

Bit[0] of any address written to the PC with a BX, BLX, LDM, LDR, or POP instruction must

be 1 for correct execution, because this bit indicates the required instruction set, and the

Cortex-M3 processor only supports thumb instructions.

3.3.3

Flexible second operand

Many general data processing instructions have a flexible second operand. This is shown

as operand2 in the descriptions of the syntax of each instruction.

Operand2 can be a:

•

Constant

•

Constant

You specify an operand2 constant in the form #constant, where constant can be:

•

Any constant that can be produced by shifting an 8-bit value left by any number of bits

within a 32-bit word.

•

Any constant of the form 0x00XY00XY

•

Any constant of the form 0xXY00XY00

•

Any constant of the form 0xXYXYXYXY

In the constants shown above, X and Y are hexadecimal digits.

In addition, in a small number of instructions, constant can take a wider range of values.

These are described in the individual instruction descriptions.

When an operand2 constant is used with the instructions MOVS, MVNS, ANDS, ORRS,

ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to bit[31] of the constant, if the

constant is greater than 255 and can be produced by shifting an 8-bit value. These

instructions do not affect the carry flag if operand2 is any other constant.

Instruction substitution

Your assembler might be able to produce an equivalent instruction in cases where you

specify a constant that is not permitted. For example, an assembler might assemble the

instruction CMP Rd, #0xFFFFFFFE as the equivalent instruction CMN Rd, #0x2.

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