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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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PM0056 数据表(PDF) 45 Page - STMicroelectronics |
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PM0056 数据表(HTML) 45 Page - STMicroelectronics |
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45 / 156 page  DocID15491 Rev 5 45/156 PM0056 The Cortex-M3 instruction set 3 The Cortex-M3 instruction set 3.1 Instruction set summary The processor implements a version of the thumb instruction set. Table 20 lists the supported instructions. In Table 20: • Angle brackets, <>, enclose alternative forms of the operand • Braces, {}, enclose optional operands • The operands column is not exhaustive • Op2 is a flexible second operand that can be either a register or a constant • Most instructions can use an optional condition code suffix For more information on the instructions and operands, see the instruction descriptions. Table 20. Cortex-M3 instructions Mnemonic Operands Brief description Flags Section ADC, ADCS {Rd,} Rn, Op2 Add with carry N,Z,C,V 3.5.1 on page 73 ADD, ADDS {Rd,} Rn, Op2 Add N,Z,C,V 3.5.1 on page 73 ADD, ADDW {Rd,} Rn, #imm12 Add N,Z,C,V 3.5.1 on page 73 ADR Rd, label Load PC-relative address — 3.4.1 on page 60 AND, ANDS {Rd,} Rn, Op2 Logical AND N,Z,C 3.5.2 on page 75 ASR, ASRS Rd, Rm, <Rs|#n> Arithmetic shift right N,Z,C 3.5.3 on page 76 B label Branch — 3.8.5 on page 92 BFC Rd, #lsb, #width Bit field clear — 3.8.1 on page 89 BFI Rd, Rn, #lsb, #width Bit field insert — 3.8.1 on page 89 BIC, BICS {Rd,} Rn, Op2 Bit clear N,Z,C 3.5.2 on page 75 BKPT #imm Breakpoint — 3.9.1 on page 98 BL label Branch with link — 3.8.5 on page 92 BLX Rm Branch indirect with link — 3.8.5 on page 92 |
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