PM0056 datasheet(33/156 Pages) STMICROELECTRONICS

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PM0056

The Cortex-M3 processor

2.3

Exception model

This section describes the exception model.

2.3.1

Exception states

Each exception is in one of the following states:

2.3.2

Exception types

The exception types are:

Inactive

The exception is not active and not pending.

Pending

The exception is waiting to be serviced by the processor. An

interrupt request from a peripheral or from software can change

the state of the corresponding interrupt to pending.

Active

An exception that is being serviced by the processor but has not

completed.

Note: An exception handler can interrupt the execution of another

exception handler. In this case both exceptions are in the active

state.

Active and pending

The exception is being serviced by the processor and there is a

pending exception from the same source.

Reset

Reset is invoked on power up or a warm reset. The exception model

treats reset as a special form of exception. When reset is asserted,

the operation of the processor stops, potentially at any point in an

instruction. When reset is deasserted, execution restarts from the

address provided by the reset entry in the vector table. Execution

restarts as privileged execution in Thread mode.

NMI

A NonMaskable Interrupt (NMI) can be signalled by a peripheral or

triggered by software. This is the highest priority exception other

than reset. It is permanently enabled and has a fixed priority of -2.

NMIs cannot be:

•

Masked or prevented from activation by any other exception

•

Preempted by any exception other than Reset.

Hard fault

A hard fault is an exception that occurs because of an error during

exception processing, or because an exception cannot be managed

by any other exception mechanism. Hard faults have a fixed priority

of -1, meaning they have higher priority than any exception with

configurable priority.

Memory management

fault

A memory management fault is an exception that occurs because of

a memory protection related fault. The fixed memory protection

constraints determines this fault, for both instruction and data

memory transactions. This fault is used to abort instruction accesses

to Execute Never (XN) memory regions.

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