PM0056 datasheet(27/156 Pages) STMICROELECTRONICS

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PM0056

The Cortex-M3 processor

The Code, SRAM, and external RAM regions can hold programs. However, it is

recommended that programs always use the Code region. This is because the processor

has separate buses that enable instruction fetches and data accesses to occur

simultaneously.

2.2.4

Software ordering of memory accesses

The order of instructions in the program flow does not always guarantee the order of the

corresponding memory transactions. This is because:

•

The processor can reorder some memory accesses to improve efficiency, providing this

does not affect the behavior of the instruction sequence.

•

The processor has multiple bus interfaces

•

Memory or devices in the memory map have different wait states

•

Some memory accesses are buffered or speculative.

Section 2.2.2: Memory system ordering of memory accesses on page 26 describes the

cases where the memory system guarantees the order of memory accesses. Otherwise, if

the order of memory accesses is critical, software must include memory barrier instructions

to force that ordering. The processor provides the following memory barrier instructions:

Use memory barrier instructions in, for example:

•

Vector table. If the program changes an entry in the vector table, and then enables the

corresponding exception, use a DMB instruction between the operations. This ensures

0xA0000000- 0xDFFFFFFF

External

device

Device(1)

XN(1) External Device memory

0xE0000000- 0xE00FFFFF

Private

Peripheral

Bus

Strongly-

ordered(1)

XN(1)

This region includes the NVIC,

System timer, and system control

block.

0xE0100000- 0xFFFFFFFF

Memory

mapped

peripherals

Device(1)

XN(1)

This region includes all the STM32

standard peripherals.

1. See Memory regions, types and attributes on page 25 for more information.

Table 12. Memory access behavior (continued)

Address

range

Memory

region

Memory

type

Description

DMB

The Data Memory Barrier (DMB) instruction ensures that outstanding

memory transactions complete before subsequent memory transactions.

See DMB on page 99.

DSB

The Data Synchronization Barrier (DSB) instruction ensures that

outstanding memory transactions complete before subsequent

instructions execute. See DSB on page 100.

ISB

The Instruction Synchronization Barrier (ISB) ensures that the effect of all

completed memory transactions is recognizable by subsequent

instructions. See ISB on page 100.

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