PM0056 datasheet(43/156 Pages) STMICROELECTRONICS

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PM0056

The Cortex-M3 processor

2.5.1

Entering sleep mode

This section describes the mechanisms software can use to put the processor into sleep

mode.

The system can generate spurious wakeup events, for example a debug operation wakes

up the processor. Therefore software must be able to put the processor back into sleep

mode after such an event. A program might have an idle loop to put the processor back to

sleep mode.

Wait for interrupt

The wait for interrupt instruction, WFI, causes immediate entry to sleep mode. When the

processor executes a WFI instruction it stops executing instructions and enters sleep mode.

See WFI on page 104 for more information.

Wait for event

The wait for event instruction, WFE, causes entry to sleep mode conditional on the value of

an one-bit event register. When the processor executes a WFE instruction, it checks this

•

If the register is 0 the processor stops executing instructions and enters sleep mode

•

If the register is 1 the processor clears the register to 0 and continues executing

instructions without entering sleep mode.

See WFE on page 103 for more information.

If the event register is 1, this indicate that the processor must not enter sleep mode on

execution of a WFE instruction. Typically, this is because an external event signal is

asserted, or a processor in the system has executed an SEV instruction, see SEV on

page 102. Software cannot access this register directly.

Sleep-on-exit

If the SLEEPONEXIT bit of the SCR is set to 1, when the processor completes the execution

of an exception handler it returns to Thread mode and immediately enters sleep mode. Use

this mechanism in applications that only require the processor to run when an exception

occurs.

2.5.2

Wakeup from sleep mode

The conditions for the processor to wakeup depend on the mechanism that cause it to enter

sleep mode.

Wakeup from WFI or sleep-on-exit

Normally, the processor wakes up only when it detects an exception with sufficient priority to

cause exception entry.

Some embedded systems might have to execute system restore tasks after the processor

wakes up, and before it executes an interrupt handler. To achieve this set the PRIMASK bit

to 1 and the FAULTMASK bit to 0. If an interrupt arrives that is enabled and has a higher

priority than current exception priority, the processor wakes up but does not execute the

interrupt handler until the processor sets PRIMASK to zero. For more information about

PRIMASK and FAULTMASK see Exception mask registers on page 19.

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