PM0056 datasheet(20/156 Pages) STMICROELECTRONICS

20 / 156 page

The Cortex-M3 processor

PM0056

20/156

DocID15491 Rev 5

To access the exception mask registers use the MSR and MRS instructions, or the CPS

instruction to change the value of PRIMASK or FAULTMASK. See MRS on page 100, MSR

on page 101, and CPS on page 98 for more information.

Priority mask register

The PRIMASK register prevents activation of all exceptions with configurable priority. See

the register summary in Table 2 on page 14 for its attributes. Figure 5 shows the bit

assignments.

Figure 5. PRIMASK bit assignments

Fault mask register

The FAULTMASK register prevents activation of all exceptions except for Non-Maskable

Interrupt (NMI). See the register summary in Table 2 on page 14 for its attributes. Figure 6

shows the bit assignments.

Figure 6. FAULTMASK bit assignments

The processor clears the FAULTMASK bit to 0 on exit from any exception handler except

the NMI handler.

Table 7. PRIMASK register bit definitions

Bits

Description

Bits 31:1

Reserved

Bit 0

PRIMASK:

0: No effect

1: Prevents the activation of all exceptions with configurable priority.

Table 8. FAULTMASK register bit definitions

Bits

Function

Bits 31:1

Reserved

Bit 0

FAULTMASK:

0: No effect

1: Prevents the activation of all exceptions except for NMI.

Reserved

PRIMASK

Reserved

FAULTMASK

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