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PM0056 数据表(PDF) 46 Page - STMicroelectronics |
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PM0056 数据表(HTML) 46 Page - STMicroelectronics |
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46 / 156 page  The Cortex-M3 instruction set PM0056 46/156 DocID15491 Rev 5 BX Rm Branch indirect — 3.8.5 on page 92 CBNZ Rn, label Compare and branch if non zero — 3.8.6 on page 93 CBZ Rn, label Compare and branch if zero — 3.8.6 on page 93 CLREX — Clear exclusive — 3.4.9 on page 71 CLZ Rd, Rm Count leading zeros — 3.5.4 on page 77 CMN, CMNS Rn, Op2 Compare negative N,Z,C,V 3.5.5 on page 78 CMP, CMPS Rn, Op2 Compare N,Z,C,V 3.5.5 on page 78 CPSID iflags Change processor state, disable interrupts — 3.9.2 on page 98 CPSIE iflags Change processor state, enable interrupts — 3.9.2 on page 98 DMB — Data memory barrier — 3.9.4 on page 100 DSB — Data synchronization barrier — 3.9.4 on page 100 EOR, EORS {Rd,} Rn, Op2 Exclusive OR N,Z,C 3.5.2 on page 75 ISB — Instruction synchronization barrier — 3.9.5 on page 100 IT — If-then condition block — 3.8.7 on page 94 LDM Rn{!}, reglist Load multiple registers, increment after — 3.4.6 on page 67 LDMDB, LDMEA Rn{!}, reglist Load multiple registers, decrement before — 3.4.6 on page 67 LDMFD, LDMIA Rn{!}, reglist Load multiple registers, increment after — 3.4.6 on page 67 LDR Rt, [Rn, #offset] Load register with word — 3.4 on page 60 LDRB, LDRBT Rt, [Rn, #offset] Load register with byte — 3.4 on page 60 LDRD Rt, Rt2, [Rn, #offset] Load register with two bytes — 3.4.2 on page 61 LDREX Rt, [Rn, #offset] Load register exclusive — 3.4.8 on page 70 Table 20. Cortex-M3 instructions (continued) Mnemonic Operands Brief description Flags Section |
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