PM0056 datasheet(73/156 Pages) STMICROELECTRONICS

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PM0056

The Cortex-M3 instruction set

3.5.1

ADD, ADC, SUB, SBC, and RSB

Add, add with carry, subtract, subtract with carry, and reverse subtract.

Syntax

op{S}{cond} {Rd,} Rn, Operand2

op{cond} {Rd,} Rn, #imm12; ADD and SUB only

where:

•

‘op’ is one of:

ADD: Add

ADC: Add with carry

SUB: Subtract

SBC: Subtract with carry

RSB: Reverse subtract

•

‘S’ is an optional suffix. If S is specified, the condition code flags are updated on the

result of the operation (see Conditional execution on page 57)

•

‘cond’ is an optional condition code (see Conditional execution on page 57)

•

‘Rd’ is the destination register. If Rd is omitted, the destination register is Rn

•

‘Rn’ is the register holding the first operand

•

‘Operand2’ is a flexible second operand (see Flexible second operand on page 52 for

details of the options).

•

‘imm12’ is any value in the range 0—4095

Operation

The ADD instruction adds the value of operand2 or imm12 to the value in Rn.

The ADC instruction adds the values in Rn and operand2, together with the carry flag.

The SUB instruction subtracts the value of operand2 or imm12 from the value in Rn.

The SBC instruction subtracts the value of operand2 from the value in Rn. If the carry flag is

clear, the result is reduced by one.

The RSB instruction subtracts the value in Rn from the value of operand2. This is useful

because of the wide range of options for operand2.

Use ADC and SBC to synthesize multiword arithmetic (see Multiword arithmetic examples

on page 74 and ADR on page 60).

ADDW is equivalent to the ADD syntax that uses the imm12 operand. SUBW is equivalent

to the SUB syntax that uses the imm12 operand.

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