PM0056 datasheet(19/156 Pages) STMICROELECTRONICS

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PM0056

The Cortex-M3 processor

Execution program status register

The EPSR contains the Thumb state bit, and the execution state bits for either the:

•

If-Then (IT) instruction

•

Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or store

multiple instruction.

See the register summary in Table 2 on page 14 for the EPSR attributes. The bit

assignments are:

Attempts to read the EPSR directly through application software using the MSR instruction

always return zero. Attempts to write the EPSR using the MSR instruction in application

software are ignored. Fault handlers can examine EPSR value in the stacked PSR to

indicate the operation that is at fault. See Section 2.3.7: Exception entry and return on

page 38

Interruptible-continuable instructions

When an interrupt occurs during the execution of an LDM or STM instruction, the processor:

•

Stops the load multiple or store multiple instruction operation temporarily

•

Stores the next register operand in the multiple operation to EPSR bits[15:12].

After servicing the interrupt, the processor:

•

Returns to the register pointed to by bits[15:12]

•

Resumes execution of the multiple load or store instruction.

When the EPSR holds ICI execution state, bits[26:25,11:10] are zero.

If-Then block

The If-Then block contains up to four instructions following a 16-bit IT instruction. Each

instruction in the block is conditional. The conditions for the instructions are either all the

same, or some can be the inverse of others. See IT on page 94 for more information.

Exception mask registers

The exception mask registers disable the handling of exceptions by the processor. Disable

exceptions where they might impact on timing critical tasks.

Table 6. EPSR bit definitions

Bits

Description

Bits 31:27

Reserved.

Bits 26:25, 15:10

ICI: Interruptible-continuable instruction bits

See Interruptible-continuable instructions on page 19.

Bits 26:25, 15:10

IT: Indicates the execution state bits of the IT instruction, see

IT on page 94.

Bit 24

Always set to 1.

Bits 23:16

Reserved.

Bits 9:0]

Reserved.

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