PM0056 datasheet(64/156 Pages) STMICROELECTRONICS

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The Cortex-M3 instruction set

PM0056

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DocID15491 Rev 5

Restrictions

In these instructions:

•

Rn must not be PC

•

Rm must be neither SP nor PC

•

Rt can be SP only for word loads and word stores

•

Rt can be PC only for word loads

When Rt is PC in a word load instruction:

•

bit[0] of the loaded value must be 1 for correct execution, and a branch occurs to this

halfword-aligned address

•

If the instruction is conditional, it must be the last instruction in the IT block.

Condition flags

These instructions do not change the flags.

Examples

STRR0, [R5, R1]; store value of R0 into an address equal to

; sum of R5 and R1

LDRSBR0, [R5, R1, LSL #1]; read byte value from an address equal to

; sum of R5 and two times R1, sign extended it

; to a word value and put it in R0

STRR0, [R1, R2, LSL #2]; stores R0 to an address equal to sum of R1

; and four times R2

3.4.4

LDR and STR, unprivileged

Load and store with unprivileged access.

Syntax

op{type}T{cond} Rt, [Rn {, #offset}]; immediate offset

where:

•

‘op’ is either LDR (load register) or STR (store register)

•

‘type’ is one of the following:

B: Unsigned byte, zero extends to 32 bits on loads

SB: Signed byte, sign extends to 32 bits (LDR only)

H: Unsigned halfword, zero extends to 32 bits on loads

SH: Signed halfword, sign extends to 32 bits (LDR only)

—: Omit, for word

•

‘cond’ is an optional condition code (see Conditional execution on page 57)

•

‘Rt’ is the register to load or store

•

‘Rn’ is the register on which the memory address is based

•

‘offset’ is an offset from Rn and can be 0 to 255. If offset is omitted, the address is the

value in Rn.

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