PM0056 datasheet(95/156 Pages) STMICROELECTRONICS

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PM0056

The Cortex-M3 instruction set

Your assembler might be able to generate the required IT instructions for conditional

instructions automatically, so that you do not need to write them yourself. See your

assembler documentation for details.

A BKPT instruction in an IT block is always executed, even if its condition fails.

Exceptions can be taken between an IT instruction and the corresponding IT block, or within

an IT block. Such an exception results in entry to the appropriate exception handler, with

suitable return information in LR and stacked PSR.

Instructions designed for use for exception returns can be used as normal to return from the

exception, and execution of the IT block resumes correctly. This is the only way that a PC-

modifying instruction is permitted to branch to an instruction in an IT block.

Restrictions

The following instructions are not permitted in an IT block:

•

CBZ and CBNZ

•

CPSID and CPSIE.

Other restrictions when using an IT block are:

•

a branch or any instruction that modifies the PC must either be outside an IT block or

must be the last instruction inside the IT block. These are:

–

ADD PC, PC, Rm

–

MOV PC, Rm

–

B, BL, BX, BLX

–

any LDM, LDR, or POP instruction that writes to the PC

–

TBB and TBH

•

Do not branch to any instruction inside an IT block, except when returning from an

exception handler

•

All conditional instructions except Bcond must be inside an IT block. Bcond can be

either outside or inside an IT block but has a larger branch range if it is inside one

•

Each instruction inside the IT block must specify a condition code suffix that is either

the same or logical inverse as for the other instructions in the block.

Your assembler might place extra restrictions on the use of IT blocks, such as prohibiting the

use of assembler directives within them.

Condition flags

This instruction does not change the flags.

Example

ITTE

; Next 3 instructions are conditional

ANDNE

R0, R0, R1

; ANDNE does not update condition flags

ADDSNE R2, R2, #1

; ADDSNE updates condition flags

MOVEQ

R2, R3

; Conditional move

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