PM0056 datasheet(39/156 Pages) STMICROELECTRONICS

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PM0056

The Cortex-M3 processor

is referred as stacking and the structure of eight data words is referred as stack frame. The

stack frame contains the following information:

•

R0-R3, R12

•

Return address

•

PSR

•

LR.

Immediately after stacking, the stack pointer indicates the lowest address in the stack frame.

Unless stack alignment is disabled, the stack frame is aligned to a double-word address. If

the STKALIGN bit of the Configuration Control Register (CCR) is set to 1, stack align

adjustment is performed during stacking.

The stack frame includes the return address. This is the address of the next instruction in

the interrupted program. This value is restored to the PC at exception return so that the

interrupted program resumes.

In parallel to the stacking operation, the processor performs a vector fetch that reads the

exception handler start address from the vector table. When stacking is complete, the

processor starts executing the exception handler. At the same time, the processor writes an

EXC_RETURN value to the LR. This indicates which stack pointer corresponds to the stack

frame and what operation mode the was processor was in before the entry occurred.

If no higher priority exception occurs during exception entry, the processor starts executing

the exception handler and automatically changes the status of the corresponding pending

interrupt to active.

If another higher priority exception occurs during exception entry, the processor starts

executing the exception handler for this exception and does not change the pending status

of the earlier exception. This is the late arrival case.

Exception return

Exception return occurs when the processor is in Handler mode and executes one of the

following instructions to load the EXC_RETURN value into the PC:

•

A POP instruction that includes the PC

•

A BX instruction with any register.

•

An LDR or LDM instruction with the PC as the destination

EXC_RETURN is the value loaded into the LR on exception entry. The exception

mechanism relies on this value to detect when the processor has completed an exception

handler. The lowest four bits of this value provide information on the return stack and

processor mode. Table 17 shows the EXC_RETURN[3:0] values with a description of the

exception return behavior.

The processor sets EXC_RETURN bits[31:4] to 0xFFFFFFF. When this value is loaded into

the PC it indicates to the processor that the exception is complete, and the processor

initiates the exception return sequence.

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