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PM0056 数据表(PDF) 131 Page - STMicroelectronics |
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PM0056 数据表(HTML) 131 Page - STMicroelectronics |
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131 / 156 page  DocID15491 Rev 5 131/156 PM0056 Core peripherals 4.4.3 Interrupt control and state register (SCB_ICSR) Address offset: 0x04 Reset value: 0x0000 0000 Required privilege: Privileged The ICSR: • Provides: – A set-pending bit for the Non-Maskable Interrupt (NMI) exception – Set-pending and clear-pending bits for the PendSV and SysTick exceptions • Indicates: – The exception number of the exception being processed – Whether there are preempted active exceptions – The exception number of the highest priority pending exception – Whether any interrupts are pending. Caution: When you write to the ICSR, the effect is unpredictable if you: • Write 1 to the PENDSVSET bit and write 1 to the PENDSVCLR bit • Write 1 to the PENDSTSET bit and write 1 to the PENDSTCLR bit. 31 3029 28 27 26 25 24 23 22 21 20 19 18 17 16 NMIPE NDSET Reserved PEND SVSET PEND SVCLR PEND STSET PENDS TCLR Reserved ISRPE NDING VECTPENDING[9:4] rw rw w rw w r rrrr r r 15 14 13 12 11 10 9 8 76 54 3 21 0 VECTPENDING[3:0] RETOB ASE Reserved VECTACTIVE[8:0] r rrrr rw rw rw rw rw rw rw rw rw |
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