TNETX3150 datasheet(22/113 Pages) TI1

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TNETX3150/TNETX3150A

ThunderSWITCH™ 15-PORT 10-/100-MBIT/S ETHERNET™ SWITCH

SPWS027F – FEBRUARY 1997 – REVISED SEPTEMBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

transmit control

Transmit control is partitioned into two blocks:

The frame-control block handles the output of data into the PHY interfaces. A number of error states are

handled. If a collision is detected, the state machine jams the output. If the collision is late (after the first

64-byte buffer has been transmitted), the frame is lost. If it is an early collision, the controller backs off before

retrying. While operating in full duplex, both carrier sense (CRS) mode and collision sensing modes are

disabled.

The FIFO-control block handles the flow of data from the FIFO buffers to the MAC interface for transmission.

The data within a FIFO buffer is cleared only after the data has been successfully transmitted without

collision (for the half-duplex ports). Transmission recovery also is handled in this state machine. If a collision

is detected, frame recovery and retransmission are initiated.

interframe-gap enforcement

The measurement reference for the interframe gap of 96

µs (when transmitting at 10 Mbit/s) is changed,

depending on frame traffic conditions. If a frame is successfully transmitted (without collision), 96

µs is

measured from MXXTXEN. If the frame suffered a collision, 96

µs is measured from MXXCRS, the

TNETX3150/TNETX3150A can receive frames with an interframe gap of less than 9.6

µs, and it always

transmits its frames with an interframe gap at 9.6

µs. The 100-Mbit/s ports can receive frames with an interframe

gap of less than 0.96

µs, and it always transmits its frames with an interframe gap of 0.96 µs.

transmit pacing

When transmit pacing is enabled, the ThunderSWITCH architecture is capable of altering its transmission

routine during times of heavy network activity. The TNETX3150/TNETX3150A is intelligent enough to sense

heavy network traffic and alter its transmission routing by intentionally inserting an extra amount of delay

between transmission attempts. The added delay reduces collision rates, and thus reduces the number of

transmission attempts, which helps reduce CPU utilization, lighten overall network traffic, and allows the

network time to normalize before attempting transmission. If the delay was not added, the

TNETX3150/TNETX3150A would attempt to transmit on an already heavily loaded network, adding to the

network traffic’s unsuccessful transmission attempts.

Each Ethernet MAC incorporates transmit-pacing logic. This is enabled on an individual basis by setting the

TXPACE bit (bit 1) of the port control registers. When set, the MACs use transmit pacing to enhance

performance (when connected on networks using other transmit-pacing-capable MACs). Transmit pacing

introduces delays into the normal transmission of frames, which delays transmission attempts between stations,

reducing the probability of collisions occurring during heavy traffic (as indicated by frame deferrals and

collisions). This increases the chance of successful transmission.

When a frame is deferred, suffers a single collision, multiple collisions, or excessive collisions, the pacing

counter is loaded with the initial value that is loaded into the PACTST register (bits 4–0). When a frame is

transmitted successfully (without experiencing a deferral, single collision, multiple collisions, or excessive

collisions), the pacing counter is decremented by one, down to zero.

With pacing enabled, and after one interframe-pacing-gap (IPG) delay, a frame is permitted to immediately

attempt transmission if the pacing counter is zero. If the pacing counter is zero, normal IPG rules apply. Pacing

delays are not inserted when the pacing counter is zero. If the pacing counter is nonzero, the frame is delayed

by the pacing delay (a delay of approximately four IPGs).

TNETX3150 数据表(PDF) 22 Page - Texas Instruments

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