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TNETX3150 数据表(PDF) 12 Page - Texas Instruments

部件名 TNETX3150
功能描述  ThunderSWITCHE 15-PORT 10-/100-MBIT/S ETHERNETE SWITCH
PDF  113 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

TNETX3150 数据表(HTML) 12 Page - Texas Instruments

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TNETX3150/TNETX3150A
ThunderSWITCH15-PORT 10-/100-MBIT/S ETHERNETSWITCH
SPWS027F – FEBRUARY 1997 – REVISED SEPTEMBER 1997
12
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions (Continued)
network monitoring (NMON) interface (see system NMON register at 0x00A2)
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
NMON00
N3
O
Network monitor bit 00. The NMON00 function is determined by the logic state of MONRXTX and
MONWIDE bits. See
system NMON register.
NMON01
N2
O
Network monitor bit 01. The NMON01 function is determined by the logic state of MONRXTX and
MONWIDE bits. See
system NMON register.
NMON02
M4
O
Network monitor bit 02. The NMON02 function is determined by the logic state of MONRXTX and
MONWIDE bits. See
system NMON register.
NMON03
M3
O
Network monitor bit 03. The NMON03 function is determined by the logic state of MONRXTX and
MONWIDE bits. See
system NMON register.
NMON04
P3
O
Network monitor bit 04. The NMON04 function is determined by the logic state of MONRXTX and
MONWIDE bits. See
system NMON register.
NMON05
P4
O
Network monitor bit 05. The NMON05 function is determined by the logic state of MONRXTX and
MONWIDE bits. See
system NMON register.
NMON06
R1
O
Network monitor bit 06. The NMON06 function is determined by the logic state of MONRXTX and
MONWIDE bits. See
system NMON register.
DRAM interface
TERMINAL
I/O
DESCRIPTION
NAME†
NO.
I/O
DESCRIPTION
DA00
A23
DA01
A24
DA02
B23
DA03
C23
O
DRAM address bus DA00 DA07 is time multiplexed with row and column address strobes
DA04
C26
O
DRAM address bus. DA00–DA07 is time multiplexed with row and column address strobes.
DA05
D24
DA06
D25
DA07
D26
DX00
E23
DX01
E24
O
DRAM extended address lines. DX00–DX02 is time multiplexed with row and column address strobes.
DX02
E26
DCAS
F23
O
DRAM column address select. DCAS is the column address strobe.
DRAS
F26
O
DRAM row address select. DRAS is the row address strobe
† DD00 is the least-significant bit.



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