TNETX3150 datasheet(38/113 Pages) TI1

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TNETX3150/TNETX3150A

ThunderSWITCH™ 15-PORT 10-/100-MBIT/S ETHERNET™ SWITCH

SPWS027F – FEBRUARY 1997 – REVISED SEPTEMBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

port statistics compilation

The port statistics are updated, depending on the frequency of updates required to maintain a constant

bandwidth to the statistics RAM. This ensures that a recordable event is not ignored.

The memory map for one port of the statistics RAM is shown in the section port statistics map.

DIO access to counter statistics

When accessing the statistics values from the DIO port, it is necessary to perform four 1-byte DIO reads, to

obtain the full 32-bit counter. To prevent the chance of the counter being updated while reading the four bytes,

the user should access the low byte first, followed by the upper three bytes. On reading the low byte, the counter

statistic value is transferred to a 32-bit holding register before being placed on the DIO bus. The register is

updated only when reading the low byte of the counter statistic. The user does not see spurious data due to an

update occurring during the read.

test access to statistics memory

Test access to the statistics RAM is provided via the DIO port after the TNETX3150/TNETX3150A has been

soft reset (or following power on before the START bit has been set). In this mode, all locations of the RAM can

be written to and read from. Once the start bit has been set, only read access is permitted to the RAM.

clearing statistics counter memory

The statistics RAM can be requested to clear at any time during operation. This is achieved by setting the

CLRSTS bit in the system control register (DIO 0xC3). This bit is latched. When set, the next statistics update

cycle writes zero to all counters in the statistics RAM before resetting the latched bit. If the CLRSTS bit has not

been reset by the user, the latched bit is set again, causing the TNETX3150/TNETX3150A to load zero into the

statistics counters again. This continues until the CLRSTS bit is reset by the user. Soft reset has no effect on

the statistics counters (their contents are not cleared during a soft reset). A hard reset causes the statistics

counters to reset to zero. Port statistics cannot be cleared on a per-port basis.

FIFO RAM access

FIFO RAM access for test is provided via the DIO interface. This allows full RAM access for RAM purposes.

User access to the FIFO is allowed only following a soft reset, but before the start bit is written (or after power

up, but before the start bit is written). The soft reset bit should be asserted then deasserted. If the soft reset bit

is not cleared, the TNETX3150/TNETX3150A holds the DRAM refresh state machine in reset and the contents

of the external memory become invalid.

EEPROM read/write

EEPROM terminals ECLK and EDIO are a direct reflection of the ECLOK and EDATA bits (SIO/XCTL register)

respectively. See

EEPROM interface for additional information.

DRAM read/write

DRAM is accessed by properly configuring the DRAM test access resistors and setting the MTEST bit at 00C2.

TNETX3150/TNETX3150A condensed DIO memory map

Table 8 illustrates the condensed DIO memory map. Each section is expanded in detail.

TNETX3150 数据表(PDF) 38 Page - Texas Instruments

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