TNETX3150 datasheet(68/113 Pages) TI1

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TNETX3150/TNETX3150A

ThunderSWITCH™ 15-PORT 10-/100-MBIT/S ETHERNET™ SWITCH

SPWS027F – FEBRUARY 1997 – REVISED SEPTEMBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

buffer allocation

Each buffer is capable of holding the complete contents of one of the internal FIFO buffers (the minimum-size

Ethernet frame). The buffers are aligned to fit within a DRAM page. No buffer crosses a page boundary, allowing

consistent access times to be attained at the expense of losing four words per 1K page boundary (each word

is 36 bits wide). The memory, organized in this way, permits fast data bursts between the internal FIFO and

external buffer memory. This reduces the amount of intermediate data management, which reduces the internal

bandwidth.

At initialization, the TNETX3150/TNETX3150A loads configuration information from the EEPROM (if present)

or uses its default reset values to set the length field for each of the queues unless initialized by DIO access.

This fixes the maximum number of buffers that a port can use for transmit queues. As buffers are used by these

queues, the length field is adjusted to indicate the number of buffers that are still allocated for use by that

particular queue (see Figure 27).

Forward Pointer

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Data

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Data

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Data

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Data

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Data

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Data

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Data

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Data

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Data

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Data

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Forward Pointer = 000000

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Data

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Data

Forward Pointer = Z

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Data

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Data

Forward Pointer = Y

Low Memory

Buffer

Addresses

High Memory

Buffer

Addresses

Free Buffer Queue Structure

(in external DRAM)

Free Queue Register

Successive

Memory

Addresses

Figure 27. Buffer Allocation

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