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TNETX3150 数据表(PDF) 39 Page - Texas Instruments |
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TNETX3150 数据表(HTML) 39 Page - Texas Instruments |
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39 / 113 page  TNETX3150/TNETX3150A ThunderSWITCH™ 15-PORT 10-/100-MBIT/S ETHERNET™ SWITCH SPWS027F – FEBRUARY 1997 – REVISED SEPTEMBER 1997 39 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TNETX3150/TNETX3150A condensed DIO memory map (continued) Table 8. TNETX3150/TNETX3150A Condensed DIO Memory Map DIO ADDRESS (BIT 15–0) SHOWN IN HEX FORMAT DESCRIPTION AREA OF TNETX3150/ TNETX3150A 0000–0077 Port 00–14 control/status and address registers† Configuration 0080–009D Port 00–14 transmit queue length† Configuration 009E–009F Reserved† Configuration 00A0 Revision register† Configuration 00A1 SIO/SCTRL register† Configuration 00A2 NMON register† Configuration 00A3 Reserved† Configuration 00A4–00C1 Port 00–14 VLAN registers† Configuration 00C2 RAM size register† Configuration 00C3 System control register† Configuration 00C4–00D3 Reserved Configuration 00D4–00D7 DRAM data Internal test 00D8 DRAM flag Internal test 00D9–00DB DRAM address Internal test 00DC Reserved Internal test 00DD DIATST Internal test 00DE–3FFF Reserved Internal test 4000–7FFF Hardware reset if written Internal test 8000–877F Port 00–14 statistics Statistics RAM 8780–87F7 Port 00–14 collisions and RX overruns Statistics RAM 87F8–87FF Reserved Statistics RAM 8800–8877 Port 00–14 TXQ registers Statistics RAM 8878–887F Reserved Statistics RAM 8880–88F7 Port 00–14 IMQ registers Statistics RAM 88F8–88FF Reserved Statistics RAM 8900–8977 Port 00–14 RXQ registers Statistics RAM 8978–9FFF Reserved Statistics RAM A000–A1FF Port 13 RX FIFO block 0–3 FIFO RAM block 3 A200–A3FF Port 13 TX FIFO block 0–3 FIFO RAM block 3 A400–A5FF Port 14 RX FIFO block 0–3 FIFO RAM block 3 A600–A7FF Port 14 TX FIFO block 0–3 FIFO RAM block 3 A800–CBFF Reserved FIFO RAM block 3 CC00-CDFF Port 00 RX FIFO block 0–3 FIFO RAM block 1 CE00–CFFF Port 00 TX FIFO block 0–3 FIFO RAM block 1 † These registers are automatically loaded from the EEPROM. |
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