TNETX3150 datasheet(64/113 Pages) TI1

64 / 113 page

TNETX3150/TNETX3150A

ThunderSWITCH™ 15-PORT 10-/100-MBIT/S ETHERNET™ SWITCH

SPWS027F – FEBRUARY 1997 – REVISED SEPTEMBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

detailed description

FIFO

The FIFO RAM provides temporary storage of network data to allow burst transfers to and from the external

DRAM, to allow network retries, and to run frame filtering.

The FIFO buffers the data between the MAC interfaces and QM block. There are independent FIFOs allocated

for transmit and receive on each port. The depth of FIFO storage is 256 bytes per port for each TX and RX

direction. Each port (256 bytes) is further subdivided into four 64-byte buffers. Each MAC access provides eight

bytes of data and one byte of flag information. The flag information is generated by the MAC interfaces and

passed with the data through the FIFO, providing useful status and control information through the

TNETX3150/TNETX3150A.

64-Bit Data + Flag

64-Byte FIFO Buffer

RX FIFO Pointer

Deserializer

Data Stream Input

MAC Interface

FIFO

FIFO Buffer

Queue

and

DRAM

Control

Queue Management Unit

(QMU)

Working Register

Free Buffer

Stack (4)

Free Queue

External DRAM

(initialized into

buffers)

Figure 23. Data Flow From MAC Interface Through the TNETX3150/TNETX3150A to External DRAM

Each of the 31 FIFO blocks is subdivided into four buffers, each holding 64 bytes of data and eight bytes of flag

information (see Figure 23). The flag byte records EOB information for the last buffer in a frame, where the buffer

can be incompletely used.

TNETX3150 数据表(PDF) 64 Page - Texas Instruments

TNETX3150 数据表(HTML) 64 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载