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TNETX3150 数据表(PDF) 9 Page - Texas Instruments |
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TNETX3150 数据表(HTML) 9 Page - Texas Instruments |
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9 / 113 page  TNETX3150/TNETX3150A ThunderSWITCH™ 15-PORT 10-/100-MBIT/S ETHERNET™ SWITCH SPWS027F – FEBRUARY 1997 – REVISED SEPTEMBER 1997 9 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions (Continued) 10-/100-Mbit/s MAC interface (ports 01–02) TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION M01COL C8 I Collision sense. Assertion of MXXCOL indicates network collision. High network collision M02COL D7 I High = network collision Low = no network collision M01CRS B8 I Carrier sense. MXXCRS indicates a frame carrier signal is being received. High frame carrier M02CRS D3 I High = frame carrier Low = no frame carrier M01PROTOCOL A8 I Interface protocol. MXXPROTOCOL indicates the protocol of the interface and is determined by the logic level on the terminal. When high, it indicates a request/grant interface for datastreaming M02PROTOCOL D1 I gg , q g g applications. When low, it indicates a CSMA/CD interface. For standard Ethernet applications, MXXPROTOCOL should be held low. M01DUPLEX C9 I/O Duplex selector. MXXDUPLEX switches the interface between full- and half-duplex operation (low half duplex high full duplex) The M01DUPLEX and M02DUPLEX inputs have active M02DUPLEX C1 I/O (low = half duplex, high = full duplex). The M01DUPLEX and M02DUPLEX inputs have active pulldown circuits used to force the outputs low when the FORCEHD bit is set. M01LINK D11 I Link selector. MXXLINK indicates the condition of the port connection. High link M02LINK D2 I High = link Low = no link M01RCLK A9 I Receive clock MXXRCLK source is from the external PHY or test device M02RCLK A3 I Receive clock. MXXRCLK source is from the external PHY or test device. M01RXDV C11 I Receive data valid. MXXRXDV indicates data on MXXRXD3–MXXRXD0 is valid. High valid data M02RXDV C4 I High = valid data Low = no valid data M01RXER B11 I Receive error. MXXRXER indicates reception of a coding error on received data. High coding error M02RXER A5 I High = coding error Low = no coding error M01RXD3 A10 M02RXD3 C5 M01RXD2 B10 Receive data Nibble receive data MXXRXD3 MXXRXD0 is from the physical media dependent M02RXD2 D5 I Receive data. Nibble receive data MXXRXD3–MXXRXD0 is from the physical media dependent (PMD) front end. Data is synchronous to MXXRCLK. If the MWIDTH bit in the port control register M01RXD1 C10 I () y g and the M00SPEED terminal are set low, then data is received on M01RXD0 and M02RXD0 terminals M02RXD1 A4 terminals. M01RXD0 D10 M02RXD0 B4 M01SPEED A11 I Bit-rate selection speed. The speed of the MAC interface is determined by the logic level on MXXSPEED. M02SPEED D6 I High = 100 Mbit/s Low = 10 Mbit/s M01TCLK C12 I Transmit clock MXXTCLK source is from the external PHY or test device M02TCLK C6 I Transmit clock. MXXTCLK source is from the external PHY or test device. |
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