TNETX3150 datasheet(50/113 Pages) TI1

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TNETX3150/TNETX3150A

ThunderSWITCH™ 15-PORT 10-/100-MBIT/S ETHERNET™ SWITCH

SPWS027F – FEBRUARY 1997 – REVISED SEPTEMBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

system control register at 0x00C3

BIT

RESET

LOAD

START

CLRSTS

STMAP

SECDIS

LONG

IOBMOD

Initial Values After Reset

BIT

NAME

FUNCTION

RESET

RESET = 1 places the TNETX3150/TNETX3150A in a software reset state. Writing a 0 clears the reset state and

allows for internal testing while keeping the ports disabled. RESET clears the port control register but does not

affect any other configuration registers. Configuration registers are cleared by a hardware reset (write to DIO

address 4000-7FFF).

LOAD

Load system. Writing a 1 to LOAD causes the TNETX3150/TNETX3150A DIO registers to auto-load from an

external EEPROM (if present). All registers in the DIO address range 0x00–0xC3 are loaded from the

corresponding EEPROM locations. Writing a 0 to LOAD has no effect. LOAD is read as a 1 until the auto-load is

complete.

LOAD is not auto-loaded. LOAD is always set to 0 by auto-load.

START

Start system. Writing a 1 to START causes the TNETX3150/TNETX3150A to begin operation. START is read as

a 1 until buffer memory initialization is complete. While buffers are being initialized, all ports are disabled. Writing

a 0 to START has no effect.

CLRSTS

Clear statistics. Writing a 1 to CLRSTS causes the TNETX3150/TNETX3150A to clear all its statistics counters.

The TNETX3150/TNETX3150A repeats clearing the statistics counters until CLRSTS is cleared.

STMAP

Statistic mapping. STMAP selects which statistic is recorded in multiple-function statistic counters. Setting STMAP

to a 1 selects the statistic to record the number of TX frames discarded on TX due to lack of resources. If STMAP

is reset to a 0, the statistic records the number of data errors at TX.

SECDIS

Disable ports on security violations. When SECDIS is set to a 1, address security violations cause a port to be

disabled. When SECDIS is set to a 0, address security violations cause a port to be suspended. Suspended ports

are reenabled when the offending condition is removed. Disabled ports can be reenabled only by management (by

setting port ENABLE bit).

LONG

Long frame handling. When LONG is set to a 1, the statistics counter for giant frames is recorded in the RX and

TX frame 1024–1518 bucket counter, which for this mode is redefined to become RX and TX frames 1024–1531.

Frames 1536 bytes or larger are truncated.

IOBMOD

IOB mode. When IOBMOD is set to a 1, broadcast/multicast frames are sent to a destination in sequence with

unicast frames from the same source port, using the IOB buffer linking mechanism. To ensure proper frame

forwarding, IOBMOD is set to a 1.

DRAM data register at 0x00D4–0x00D7

BIT

DRAM DATA

BIT

NAME

FUNCTION

31–0

DRAM DATA

DRAM Data. DRAM DATA holds a 32-bit data value that maps to the forward pointer field of a DRAM buffer

when accessed in DRAM test-access mode.

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