TNETV1644ZDU6 datasheet(2/306 Pages) TI1

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TMS320DM6437

Digital Media Processor

SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008

www.ti.com

–

Supports Media Independent Interface (MII)

• Enhanced Direct-Memory-Access (EDMA)

–

Management Data I/O (MDIO) Module

Controller (64 Independent Channels)

• VLYNQ™ Interface (FPGA Interface)

• Two 64-Bit General-Purpose Timers (Each

Configurable as Two 32-Bit Timers)

• Three Pulse Width Modulator (PWM) Outputs

• One 64-Bit Watch Dog Timer

• On-Chip ROM Bootloader

• Two UARTs (One with RTS and CTS Flow

• Individual Power-Savings Modes

Control)

• Flexible PLL Clock Generators

• Master/Slave Inter-Integrated Circuit (I2C

• IEEE-1149.1 (JTAG™)

Bus™)

Boundary-Scan-Compatible

• Two Multichannel Buffered Serial Ports

• Up to 111 General-Purpose I/O (GPIO) Pins

(McBSPs)

(Multiplexed With Other Device Functions)

–

I2S and TDM

• Packages:

–

AC97 Audio Codec Interface

–

361-Pin Pb-Free PBGA Package

–

SPI

(ZWT Suffix), 0.8-mm Ball Pitch

–

Standard Voice Codec Interface (AIC12)

–

376-Pin Plastic BGA Package

–

Telecom Interfaces – ST-Bus, H-100

(ZDU Suffix), 1.0-mm Ball Pitch

–

128 Channel Mode

• 0.09-µm/6-Level Cu Metal Process (CMOS)

• Multichannel Audio Serial Port (McASP0)

• 3.3-V and 1.8-V I/O, 1.2-V Internal

–

Four Serializers and SPDIF (DIT) Mode

(-7/-6/-5/-4/-L/-Q6/-Q5/-Q4)

• 16-Bit Host-Port Interface (HPI)

• 3.3-V and 1.8-V I/O, 1.05-V Internal

• High-End CAN Controller (HECC)

(-7/-6/-5/-4/-L/-Q5)

• 32-Bit 33-MHz, 3.3-V Peripheral Component

• Applications

Interconnect (PCI) Master/Slave Interface

–

Digital Media

• 10/100 Mb/s Ethernet MAC (EMAC)

–

Networked Media Encode/Decode

–

IEEE 802.3 Compliant

–

Video Imaging

TMS320DM6437 Digital Media Processor

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