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TNETV1644ZDU6 数据表(PDF) 100 Page - Texas Instruments |
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TNETV1644ZDU6 数据表(HTML) 100 Page - Texas Instruments |
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100 / 306 page  HostBlock(27pins) (A)(C) PCI(27) PCIEN=1 HOSTBK=000 GPIO(27) PCIEN=0 HOSTBK=000 VLYNQ (10) GPIO(17) VLYNQ (10) EMAC(15) MDIO (2) PCIEN=0 HOSTBK=001 PCIEN=0 HOSTBK=010 PCIEN=0 HOSTBK=011 PCIEN=0 HOSTBK=100 HPI(26) GPIO(1) EMAC(15) MDIO (2) GPIO(10) GPIOBlock(4pins) (C) PCI (4) PCIEN=1 GPIO (4) PCIEN=0 UART0DataBlock(2pins) GPIO(2) UR0DBK=0 UART Data(2) UR0DBK=1 UART0FlowControlBlock(2pins) GPIO(2) UR0FCBK=00 UART0 FlowCtrl(2) UR0FCBK=01 PWM0(1) UR0FCBK=10 GPIO(1) Timer1Block(2pins) GPIO(2) TIM1BK=00 Timer1 (2) TIM1BK=01 UART1 Data(2) TIM1BK=10 HECC (2) TIM1BK=11 Timer0Block(2pins) (D)(E) GPIO(2) TIM0BK=00 Timer0 (2) TIM0BK=01 McBSP0 CLKS0(1) TIM0BK=10 McBSP1 CLKS1(1) McBSP0 CLKS0(1) TIM0BK=11 Timer0 TINPOL (1) PWM1Block(1pin) GPIO (1) PWM1BK=0 PWM1 (1) PWM1BK=1 CLKOUTBlock(1pin) GPIO (1) CKOBK=00 CLKOUT (1) CKOBK=01 PWM2 (1) CKOBK=10 SerialPortSub-Block0(6pins) (D) GPIO(6) SPBK0=00 McBSP0 (6) SPBK0=01 McASP0Receive and3Serializers(6) SPBK0=10 SerialPortSub-Block1(6pins) (E) GPIO(6) SPBK1=00 McBSP1 (6) SPBK1=01 McASP0 Transmitand 1Serializer(6) SPBK1=10 McBSP1 Transmit(3) SPBK1=11 McASP0 SPDIF(3) EMIFA/VPSSBlock(61pins) (A)(B)(C) 8-24b VPBE MajorConfig Option A 8-16b VPFE GPIO 8-24b VPBE MajorConfig OptionF 8b VPFE GPIO PCI 8b VPBE MajorConfig OptionB GPIO 8-16b VPFE 8bEMIFA (Async) Pinout Mode1 32KB-16MB perCE 8-16b VPBE MajorConfig OptionC GPIO 8b VPFE 8bEMIFA (Async) Pinout Mode3 32KBper CE 8-16b VPBE MajorConfig OptionD GPIO 8b VPFE 8bEMIFA (NAND) Pinout Mode4 8b VPBE MajorConfig OptionE GPIO 8-16b VPFE 8bEMIFA (NAND) Pinout Mode5 8b VPBE MajorConfig OptionG GPIO 8b VPFE 8bEMIFA (NAND) Pinout Mode5 PCI PCIDataBlock(3pins) (C) PCI(3) Notmuxed AEM=000, PCIEN=0 AEM=001, PCIEN=0 AEM=011, PCIEN=0 AEM=100, PCIEN=0 AEM=101, PCIEN=0 AEM=000, PCIEN=1 AEM=101, PCIEN=1 TMS320DM6437 Digital Media Processor SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008 www.ti.com A. Default settings for PINMUX0 and PINMUX1 registers are underlined. B. EMIFA/VPSS Block: shows the Major Config Options based on the AEM and PCIEN settings. Actual pin functions in the EMIFA/VPSS Block are further determined by other PINMUX fields. C. PCI pins span multiple blocks (Host Block, GPIO Block, EMIFA/VPSS Block, and PCI Data Block). For PCI to be operational, PCI pins must be selected in all of these Pin Mux Blocks. For the EMIFA/VPSS Block, PCI is only supported if AEM = 000b or 101b. D. McBSP0 pins span multiple blocks (Serial Port Sub-Block0 and Timer0 Block). Serial Port Sub-Block0 contains most of the pins needed for McBSP0 operation. Timer0 Block contains the optional external clock source input CLKS0. E. McBSP1 spans multiple blocks (Serial Port Sub-Block1, Timer0 Block). Serial Port Sub-Block1 contains most of the pins needed for McBSP1 operation. Timer0 Block contains the optional external clock soruce input CLKS1. Figure 3-11. Pin Mux Block Selection Device Configurations 100 Submit Documentation Feedback |
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