TNETV1644ZDU6 datasheet(89/306 Pages) TI1

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TMS320DM6437

Digital Media Processor

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SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008

Table 3-9. BOOTCFG Register Description

Bit

Field Name

Description

31:20

RESERVED

Reserved. Writes have no effect.

Fastboot (see Section 3.4.1.1, FASTBOOT)

This field is used by the device bootloader code to determine if it needs to speed up the device to PLL mode

before booting.

FASTBOOT

0 = No Fastboot

1 = Fastboot

The default value is latched from FASTBOOT configuration pin.

RSV

Reserved. Writes have no effect.

PINMUX1.PCIEN Default (see Section 3.5.1.3, PCI Enable)

For more details on the PCIEN settings, see Section 3.7.2.2, PINMUX1 Register Description.

This field affects the pin mux control by setting the default of PINMUX1.PCIEN. This field determines if the

internal pullup/pulldown resistors on the PCI capable pins are enabled/disabled. This field does not affect PCI

DPCIEN

The user must keep the value on the PCIEN pin constant throughout the operation.

The default value is from the PCIEN configuration pin.

16:15

RSV

Reserved. Writes have no effect.

PINMUX0.AEAW default [AEAW] and Fastboot PLL Multiplier Select [PLLMS] (see Section 3.5.1.2, EMIFA

Address Width Select [AEAW] and Fast Boot PLL Multiplier Select [PLLMS])

The AEAW[2:0]/PLLMS configuration pins serve two purposes:

AEAW[2:0]: 8-bit EMIFA (Async) Pinout Mode 1 Address Width

If AEM = 001, this field serves as AEAW and it indicates the 8-bit EMIFA (Async) Pinout Mode 1 Address

Width. In this case, this field affects pin mux control only by setting the default of Pin Mux Control Register

14:12

PLLMS

PINMUX0.AEAW[2:0]. This field does not affect EMIFA register settings.

For more details on the AEAW settings, see Section 3.7.2.1, PINMUX0 Register Description.

PLLMS: Fastboot PLL Multiplier Select

If FASTBOOT = 1 and AEM[2:0] = 000b, 011b, 100b, or 101b, this field selects the FASTBOOT PLL Multiplier.

In this case, this field does not affect the pin mux control or the EMIFA register settings. The bootloader code

uses this field to determine the PLL multiplier used for Fastboot.

RSV

Reserved. Writes have no effect.

PINMUX0.AEM default [DAEM] (see Section 3.5.1.1, EMIFA Pinout Mode (AEM[2:0]))

For more details on the AEM settings, see Section 3.7.2.1, PINMUX0 Register Description.

10:8

DAEM

This field affects pin mux control by setting the default of PINMUX0.AEM. This field does not affect EMIFA

The default value is latched from the AEM[2:0] configuration pins.

7:4

RESERVED

Reserved. Writes have no effect.

Boot Mode (see Section 3.4.1, Boot Modes)

This field is used in conjunction with FASTBOOT, PCIEN, AEM, and PLLMS to determine the device boot

3:0

BOOTMODE

mode.

The default value is latched from the BOOTMODE[3:0] configuration pins.

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