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TNETV1644ZDU6 数据表(PDF) 49 Page - Texas Instruments |
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TNETV1644ZDU6 数据表(HTML) 49 Page - Texas Instruments |
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49 / 306 page ![]() TMS320DM6437 Digital Media Processor www.ti.com SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008 Table 2-18. Host-Port Interface Terminal Functions SIGNAL TYPE(1) OTHER(2)(3) DESCRIPTION ZWT ZDU NAME NO. NO. Host-Port Interface (HPI) HD0/VLYNQ_SCRUN/ IPU C8 B9 AD18/GP[58] DVDD33 HD1/VLYNQ_RXD0/ D7 C9 AD16/GP[59] HD2/VLYNQ_RXD1/ A8 A9 AD17/GP[60] HD3/VLYNQ_RXD2/ B7 B8 PCBE2/GP[61] HD4/VLYNQ_RXD3/ C7 C8 PFRAME/GP[62] HD5/VLYNQ_TXD0/ A6 A7 PIRDY/GP[63] HD6/VLYNQ_TXD1/ D6 C7 PTRDY/GP[64] This pin is multiplexed between HPI, VLYNQ or EMAC, PCI, HD7/VLYNQ_TXD2/ B6 B7 and GPIO. PDEVSEL/GP[65] I/O/Z In HPI mode, these pins are host-port data pins HD[15:0] HD8/VLYNQ_TXD3/ IPD (I/O/Z) and are multiplexed internally with the HPI address A5 A6 PPERR/GP[66] DVDD33 lines. HD9/MCOL/ C6 C6 PSTOP/GP[67] HD10/MCRS/ B5 B6 PSERR/GP[68] HD11/MTXD3/ C5 A5 PCBE1/GP[69] HD12/MTXD2/ D5 C5 PPAR/GP[70] HD13/MTXD1/ B4 B4 AD14/GP[71] HD14/MTXD0/ D4 B5 AD15/GP[72] HD15/MTXCLK/ A4 A4 AD12/GP[73] This pin is multiplexed between HPI, EMAC, PCI, and GPIO. HHWIL/MRXDV/ IPD C4 D3 I/O/Z In HPI mode, this pin is half-word identification input HHWIL AD13/GP[74] DVDD33 (I). This pin is multiplexed between HPI, EMAC, PCI, and GPIO. In HPI mode, this pin is control input 1 HCNTL1 (I). The state HCNTL1/MTXEN/ IPD D3 C4 I/O/Z of HCNTL1 and HCNTL0 determines if address, data, or AD11/GP[75] DVDD33 control information is being transmitted between an external host and the DM6437. This pin is multiplexed between HPI, EMAC, PCI, and GPIO. In HPI mode, this pin is control input 0 HCNTL0 (I). The state HCNTL0/MRXER/ IPD B3 B2 I/O/Z of HCNTL1 and HCNTL0 determines if address, data, or AD10/GP[76] DVDD33 control information is being transmitted between an external host and the DM6437. This pin is multiplexed between HPI, EMAC, PCI, and GPIO. HR/W/MRXCLK/ IPD A3 A3 I/O/Z In HPI mode, this pin is host read or write select input AD8/GP[77] DVDD33 HR/W(I). HDS2/MRXD0/ IPU This pin is multiplexed between HPI, EMAC, PCI, and GPIO. C3 C2 I/O/Z AD9/GP[78] DVDD33 In HPI mode, this pin is host data strobe input 2 HDS2 (I). (1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal (2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.9.1, Pullup/Pulldown Resistors. (3) Specifies the operating I/O supply voltage for each signal Submit Documentation Feedback Device Overview 49 |
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