TNETV1644ZDU6 datasheet(36/306 Pages) TI1

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TMS320DM6437

Digital Media Processor

SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008

www.ti.com

Table 2-11. EMIFA Terminal Functions (EMIFA Pinout Mode 3, AEM[2:0] = 011) (continued)

SIGNAL

TYPE(1)

OTHER(2)(3)

DESCRIPTION

ZWT

ZDU

NAME

NO.

This pin is multiplexed between VPBE (VENC), EMIFA, and GPIO.

B0/LCD_FIELD/

IPD

B18

D21

I/O/Z

EM_A[3]/GP[11]

DVDD33

For EMIFA, it is address bit 3 output EM_A[3].

B1/EM_A[2]/

This pin is multiplexed between VPBE (VENC), EMIFA, and GPIO.

IPD

(CLE)/GP[8]/

B16

A20

I/O/Z

DVDD33

For EMIFA, it is address bit 2 output EM_A[2].

(AEAW0/PLLMS0)

G1/EM_A[1]/

This pin is multiplexed between VPBE (VENC), EMIFA, and GPIO.

IPD

(ALE)/GP[9]/

A16

B20

I/O/Z

DVDD33

For EMIFA, it is address output EM_A[1].

(AEAW1/PLLMS1)

This pin is multiplexed between VPBE (VENC), EMIFA, and GPIO.

For EMIFA, this is Address output EM_A[0], which is the least

R1/ EM_A[0]/

IPD

B17

C21

I/O/Z

significant bit on a 32-bit word address.

GP[7]/(AEM2)

DVDD33

For an 8-bit asynchronous memory, this pin is the 3rd bit of the

address.

EMIFA FUNCTIONAL PINS: 8-Bit NAND (EMIFA Pinout Mode 3, AEM[2:0] = 011)

This pin is multiplexed between VPBE (VENC), EMIFA (NAND), and

G1/EM_A[1]/

GPIO.

IPD

(ALE)/GP[9]/

A16

B20

I/O/Z

DVDD33

When used for EMIFA (NAND) , this pin is the Address Latch Enable

(AEAW1/PLLMS1)

output (ALE).

This pin is multiplexed between VPBE (VENC), EMIFA (NAND), and

B1/EM_A[2]/

GPIO.

IPD

(CLE)/GP[8]/

B16

A20

I/O/Z

DVDD33

When used for EMIFA (NAND) , this pin is the Command Latch

(AEAW0/PLLMS0)

Enable output (CLE).

EM_WAIT/

IPU

E15

D20

I/O/Z

When used for EMIFA (NAND), it is ready/busy input (RDY/BSY).

(RDY/BSY)

DVDD33

IPU

EM_OE

D15

D19

I/O/Z

When used for EMIFA (NAND), this pin is read enable output (RE).

DVDD33

IPU

EM_WE

E14

C19

I/O/Z

When used for EMIFA (NAND), this pin is write enable output (WE).

DVDD33

This pin is multiplexed between VPBE (VENC), EMIFA (NAND), and

GPIO.

For EMIFA, this pin is Chip Select 2 output EM_CS2 for use with

NAND flash.

G0/EM_CS2/

IPD

C19

C22

I/O/Z

This is the chip select for the default boot and ROM boot modes.

GP[12]

DVDD33

Note: This pin features an internal pulldown (IPD). If this pin is

connected and used as an EMIFA chip select signal, for proper device

operation, an external pullup resistor must be used to ensure the

EM_CSx function defaults to an inactive (high) state.

This pin is multiplexed between VPBE (VENC), EMIFA (NAND), and

GPIO.

For EMIFA, this pin is Chip Select 3 output EM_CS3 for use with

LCD_OE/EM_CS3/

IPD

NAND flash.

C18

D22

I/O/Z

GP[13]

DVDD33

Note: This pin features an internal pulldown (IPD). If this pin is

connected and used as an EMIFA chip select signal, for proper device

operation, an external pullup resistor must be used to ensure the

EM_CSx function defaults to an inactive (high) state.

This pin is multiplexed between VPBE (VENC), EMIFA (NAND), and

GPIO.

For EMIFA, it is Chip Select 4 output EM_CS4 for use with NAND

VSYNC/EM_CS4/

IPD

flash.

E19

H22

I/O/Z

GP[32]

DVDD33

Note: This pin features an internal pulldown (IPD). If this pin is

connected and used as an EMIFA chip select signal, for proper device

operation, an external pullup resistor must be used to ensure the

EM_CSx function defaults to an inactive (high) state.

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